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    폴리머 후막 저항체 형성 방법
    51.
    发明授权
    폴리머 후막 저항체 형성 방법 失效
    聚合物厚膜电阻的形成方法

    公开(公告)号：KR100903967B1

    公开(公告)日：2009-06-25

    申请号：KR1020070076705

    申请日：2007-07-31

    Applicant: 전자부품연구원

    Inventor： 박성대 ,  박세훈 ,  유명재

    IPC: H01L21/027

    Abstract: 본 발명은 폴리머 후막 저항체 형성 방법에 관한 것으로, 전도성부가 형성된 기판 위에 감광성 저항용 페이스트를 도포시 종래와 같은 스크린 인쇄 방식을 이용하지 않고, 감광성 저항용 페이스트가 구비된 핸드 롤러 또는 롤 코터 등을 이용한 롤 코팅 방식으로 상기 감광성 저항용 페이스트를 도포함으로써 기판 내 두께 편차를 줄이고, 최종 경화 후 저항치의 허용편차가 작은 폴리머 후막 저항체를 형성하는 방법에 대한 것이다.
    감광, 저항체, 페이스트, 편차

    다이플렉서
    52.
    发明授权
    다이플렉서 失效
    双工器

    公开(公告)号：KR100862886B1

    公开(公告)日：2008-10-13

    申请号：KR1020070050872

    申请日：2007-05-25

    Applicant: 전자부품연구원

    Inventor： 유찬세 ,  박세훈 ,  이우성 ,  김준철 ,  강남기

    IPC: H01P1/213

    CPC classification number: H01P1/213 ,  H01P1/2088 ,  H01P9/02 ,  H03H7/463

    Abstract: A diplexer is provided to reduce parasitic capacitance by forming an inductor pattern on a low dielectric constant organic substrate and to reduce a size by forming a capacitor pattern on a high dielectric constant organic substrate. A diplexer includes a low pass filter(300) and a high pass filter(310). The low pass filter is positioned between an antenna terminal(ANT) and a first band duplexer. The high pass filter is positioned between the antenna terminal and a second band duplexer. The low pass filter has a matching inductor(L11) and a first series resonator(302). The matching inductor is connected between the antenna terminal and the first band duplexer to pass a low band signal. The first series resonator is connected between a connection point of the first band duplexer and the matching inductor and a ground. The high pass filter has a matching capacitor(C12) and a second series resonator(312). The matching capacitor is connected between the antenna terminal and the second band duplexer to pass a high band signal. The second series resonator is connected between a connection point of the second band duplexer and the matching capacitor and a ground.

    Abstract translation: 提供双工器以通过在低介电常数有机衬底上形成电感器图案来减小寄生电容，并通过在高介电常数有机衬底上形成电容器图案来减小尺寸。 双工器包括低通滤波器（300）和高通滤波器（310）。 低通滤波器位于天线端子（ANT）和第一频带双工器之间。 高通滤波器位于天线端子和第二频带双工器之间。 低通滤波器具有匹配电感器（L11）和第一串联谐振器（302）。 匹配电感器连接在天线端子和第一频带双工器之间以通过低频带信号。 第一串联谐振器连接在第一频带双工器的连接点和匹配电感器和地之间。 高通滤波器具有匹配电容器（C12）和第二串联谐振器（312）。 匹配电容器连接在天线端子和第二频带双工器之间以通过高频带信号。 第二串联谐振器连接在第二频带双工器的连接点和匹配电容器和地之间。

    칩 내장형 인쇄회로기판 및 그 제조방법
    53.
    发明授权
    칩 내장형 인쇄회로기판 및 그 제조방법 失效
    芯片嵌入式印刷电路板及其制作方法

    公开(公告)号：KR100816324B1

    公开(公告)日：2008-03-24

    申请号：KR1020070050202

    申请日：2007-05-23

    Applicant: 전자부품연구원

    Inventor： 박세훈 ,  김준철 ,  박종철 ,  강남기 ,  이우성 ,  유찬세

    IPC: H05K3/30 ,  H05K1/18

    CPC classification number: H05K1/187 ,  H01L2224/16 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/162 ,  H05K1/186 ,  H05K3/0061 ,  H05K3/1291 ,  H05K3/205 ,  H05K3/207 ,  H05K3/3436 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/0376 ,  H05K2203/0733 ,  H05K2203/1126 ,  H01L2224/0401

    Abstract: A chip embedded printed circuit board and a fabricating method thereof are provided to stably treat the printed circuit board during a fabricating process by using a support layer of sufficient thickness to perform packaging in a very flat state. A fabricating method of a chip embedded printed circuit board includes the steps of: forming a first circuit pattern(115) on a top of a support layer; mounting a semiconductor chip(120) on the first circuit pattern; forming an insulation layer(130) on the top of the support layer to surround the first circuit pattern and the semiconductor chip and forming a metal layer on a top of the insulation layer; forming a via hole(150) passing through the insulation layer and the metal layer on the first circuit pattern and forming a plating layer(155) on an inner wall of the via hole; forming a second circuit pattern(145) on the top of the insulation layer by etching the metal layer; and forming a radiation plate(200) by removing the support layer in a region except a lower region of the semiconductor chip.

    Abstract translation: 提供一种芯片嵌入式印刷电路板及其制造方法，以在制造过程中通过使用足够厚度的支撑层在非常平坦的状态下进行包装来稳定地处理印刷电路板。 芯片嵌入式印刷电路板的制造方法包括以下步骤：在支撑层的顶部上形成第一电路图案（115）; 将半导体芯片（120）安装在所述第一电路图案上; 在所述支撑层的顶部上形成绝缘层（130），以围绕所述第一电路图案和所述半导体芯片，并在所述绝缘层的顶部上形成金属层; 形成穿过所述绝缘层和所述第一电路图案上的所述金属层的通孔（150），并在所述通孔的内壁上形成镀层（155）; 通过蚀刻金属层在绝缘层的顶部上形成第二电路图案（145）; 以及通过在除了所述半导体芯片的下部区域之外的区域中去除所述支撑层而形成辐射板（200）。

    저유전율 저손실의 열경화성 복합 수지 조성물
    54.
    发明公开
    저유전율 저손실의 열경화성 복합 수지 조성물 有权
    具有低介电常数和低介电损耗的热固性复合树脂

    公开(公告)号：KR1020080015273A

    公开(公告)日：2008-02-19

    申请号：KR1020060076775

    申请日：2006-08-14

    Applicant: 전자부품연구원

    Inventor： 유명재 ,  박성대 ,  이우성 ,  박세훈 ,  임진규

    IPC: C08L71/12 ,  C08L25/06

    Abstract: A thermosetting composite resin composition having a low dielectric constant and a low dielectric loss is provided to be used in forming a laminate for printed circuits and to ensure transmission characteristics suitable for a high-frequency band. A thermosetting composite resin composition having a low dielectric constant and a low dielectric loss includes: a base resin obtained by mixing polyphenylene oxide with polystyrene in a weight ratio of 6:4 to 8:2; a crosslinking agent in a sufficient amount to provide a weight ratio of 1:9 to 3:7 based on the base resin; an additive in a sufficient amount to provide a weight ratio of 1:10 to 1:5 based on the base resin; and an initiator in a sufficient amount to provide a weight ratio of 1:20 to 1:5 based on the crosslinking agent.

    Abstract translation: 提供具有低介电常数和低介电损耗的热固性复合树脂组合物，用于形成印刷电路用层压体并确保适用于高频带的传输特性。 具有低介电常数和低介电损耗的热固性复合树脂组合物包括：通过将聚苯醚与聚苯乙烯以6:4至8:2的重量比混合而获得的基础树脂; 足够量的交联剂，以基于树脂的比例提供1:9至3:7的重量比; 足够量的添加剂，以基于树脂的比例提供1:10至1:5的重量比; 和足量的引发剂，以提供基于交联剂的1:20至1:5的重量比。

    3차원 패키징 모듈
    56.
    发明授权
    3차원 패키징 모듈 有权
    三维包装模块

    公开(公告)号：KR101404014B1

    公开(公告)日：2014-06-27

    申请号：KR1020120136488

    申请日：2012-11-28

    Applicant: 전자부품연구원

    Inventor： 박종철 ,  박세훈 ,  유종인

    IPC: H01L25/16 ,  H01L23/64

    CPC classification number: H01L2224/16225 ,  H01L2924/1532

    Abstract: 본 발명은 3차원 패키징 모듈에 대하여 개시한다. 본 발명의 일 면에 따른 3차원 패키징 모듈은, 복수의 층으로 구성되며, 상기 복수의 층 중 어느 한 층에서 내장된 인덕터를 포함하는 인터포저, 상기 인터포저의 하부면 상에 형성된 TMV(Through Mold Via)들 사이에 배치되어 상기 인터포저의 하부면에 실장되는 IC 및 상기 인덕터가 내장된 층과 다른 층에서 형성되어 상기 인덕터와 상기 IC를 연결하는 패턴을 포함하는 인터포저 모듈; 및 상기 IC와 연결되는 커패시터가 내장되며, 실장용 패드(PAD)을 포함하는 인쇄회로기판을 포함한다.

    3차원 패키징 모듈
    57.
    发明公开
    3차원 패키징 모듈 有权
    三维包装模块

    公开(公告)号：KR1020140068690A

    公开(公告)日：2014-06-09

    申请号：KR1020120136488

    申请日：2012-11-28

    Applicant: 전자부품연구원

    Inventor： 박종철 ,  박세훈 ,  유종인

    IPC: H01L25/16 ,  H01L23/64

    CPC classification number: H01L2224/16225 ,  H01L2924/1532

    Abstract: A three-dimensional packaging module is disclosed. The three-dimensional packaging module, according to an aspect of the present invention, comprises: an interposer including a connecting member in which IC and an inductor connected to the IC are equipped; and a printed circuit board including a pad for mounting in which a capacitor connected to the IC is equipped. The connecting member and the pad for mounting are configured with a number and a shape corresponding to each other to form, when connected to each other through soldering, the IC and a peripheral circuit of the IC including the inductor and the capacitor as a one module by electrically connecting the IC with at least one of the inductor and the capacitor.

    Abstract translation: 公开了三维封装模块。 根据本发明的一个方面的三维封装模块包括：插入器，包括连接IC和连接到IC的电感器的连接构件; 以及印刷电路板，其包括用于安装的焊盘，其中配备有连接到IC的电容器。 连接构件和用于安装的焊盘构造成具有相互对应的数量和形状，以通过焊接将IC和包括电感器和电容器的IC的外围电路作为一个模块形成 通过将IC与电感器和电容器中的至少一个电连接。

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