-
公开(公告)号：KR1020150108981A
公开(公告)日：2015-10-01
申请号：KR1020140031644
申请日：2014-03-18
Applicant: 한국전자통신연구원
CPC classification number: H03H7/38 , H01L23/642 , H01L2224/49175 , H01P1/2039 , H01P5/12 , H05K1/025 , H05K2201/09781 , H01L23/04 , H01L24/14 , H04B1/44
Abstract: 본발명에서는정합회로를포함하는소자패키지및 그것의정합방법을제공한다. 본발명에따른소자패키지는정합부를포함하고, 정합부는기판, 기판에형성되고소자패키지의단자와연결되는전송선로, 전송선로와중심소자를전기적으로연결하는본딩와이어및 배선연결을통해전송선로와전기적으로연결되는복수의캐패시터를구비한캐패시터부를포함하고, 본딩와이어의길이조정을통해정합부의인덕턴스가가변되고, 배선연결의연장또는차단을통해캐패시터부중 전송선로와전기적으로연결되는캐패시터들의수를증가또는감소시킴으로써정합부의캐패시턴스가가변된다.
Abstract translation: 提供具有匹配电路的装置封装及其匹配方法。 装置包装包括匹配单元。 匹配单元包括：基板; 形成在所述基板上并连接到所述器件封装的端子的传输线; 用于将传输线与中央设备电连接的接合线; 以及具有多个电容器的电容器单元，其通过线路连接与传输线电连接。 通过调整接合线的长度来改变匹配单元的电感。 匹配单元的电容通过延长或阻止线路连接来增加或减少电连接到电容器单元中的传输线的电容器的数量而改变。
-
公开(公告)号：KR1020140080575A
公开(公告)日：2014-07-01
申请号：KR1020120144129
申请日：2012-12-12
Applicant: 한국전자통신연구원
CPC classification number: H01L23/66 , H01L23/49844 , H01L2223/6655 , H01L2224/48091 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
Abstract: A package is provided. The package includes a chip plate, a chip mounting plate which is arranged in one side of a ground plate and has an upper surface which is lower than the ground plate, a chip which is mounted on the chip mounting plate, a first input/output terminal which faces the chip mounting plate, is arranged in one side of the ground plate, and is electrically connected to the chip, and a second input/output terminal which faces the ground plate, is arranged in the other side of the chip mounting plate, and is electrically connected to the chip.
Abstract translation: 提供一个包装。 该封装包括芯片板，芯片安装板，其布置在接地板的一侧并具有比接地板低的上表面，安装在芯片安装板上的芯片，第一输入/输出 面向芯片安装板的端子布置在接地板的一侧，并且电连接到芯片，并且面对接地板的第二输入/输出端子布置在芯片安装板的另一侧 并且电连接到芯片。
-
公开(公告)号：KR1020140079539A
公开(公告)日：2014-06-27
申请号：KR1020120146836
申请日：2012-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: The present invention relates to a transistor and a method of fabricating the same. A field effect transistor according to one embodiment of the present invention includes a source electrode and a drain electrode which are separated from each other on a substrate; and a + type gate electrode which is arranged on the substrate between the source electrode and the drain electrode. According to one embodiment of the present invention, the + type gate electrode includes a T type gate electrode part; and an additional gate electrode part.
Abstract translation: 晶体管及其制造方法技术领域本发明涉及晶体管及其制造方法。 根据本发明的一个实施例的场效应晶体管包括在基板上彼此分离的源电极和漏电极; 以及配置在源电极和漏电极之间的基板上的+型栅电极。 根据本发明的一个实施例，+型栅电极包括T型栅电极部分; 和附加的栅电极部分。
-
公开(公告)号：KR1020130085224A
公开(公告)日：2013-07-29
申请号：KR1020120006224
申请日：2012-01-19
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to improve the stability of a T-type gate electrode by providing the high electron mobility transistor including an insulating film having a fine critical dimension. CONSTITUTION: A source electrode (202a) and a drain electrode (202b) are formed on a substrate (201). Insulating layers (203,206,208) including an opening part (209) between the source electrode and drain electrode are formed. The insulating layer comprises silicon nitride film or silicon oxide film. A T-type gate electrode (213) is formed at the upper part of the insulating layer. The body part of the T-type gate electrode is formed at the opening part of the insulating film.
Abstract translation: 目的：提供一种高电子迁移率晶体管及其制造方法，通过提供包括具有细小临界尺寸的绝缘膜的高电子迁移率晶体管来提高T型栅电极的稳定性。 构成：在基板（201）上形成源电极（202a）和漏电极（202b）。 形成包括源电极和漏电极之间的开口部分（209）的绝缘层（203,206,208）。 绝缘层包括氮化硅膜或氧化硅膜。 在绝缘层的上部形成T型栅电极（213）。 T型栅极的主体部分形成在绝缘膜的开口部分。
-
公开(公告)号：KR1020130077432A
公开(公告)日：2013-07-09
申请号：KR1020110146139
申请日：2011-12-29
Applicant: 한국전자통신연구원
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: PURPOSE: An automatic gain control feedback amplifier is provided to freely control a gain even when a difference of an input signal is great. CONSTITUTION: An automatic gain control feedback amplifier (200) includes an amplifier circuit (210), a feedback circuit (220), and a bias circuit (230). The amplifier circuit amplifies a voltage inputted from an input terminal and outputs the voltage to an output terminal. The feedback circuit is connected between the input terminal and the output terminal. The feedback circuit includes a feedback resistor part (221) whose total voltage value is determined by one or more control signals and a feedback transistor connected to the feedback resistor part in parallel. The bias circuit provides a predetermined bias voltage to the feedback transistor.
Abstract translation: 目的：提供一种自动增益控制反馈放大器，即使当输入信号的差异大时也能自由地控制增益。 构成：自动增益控制反馈放大器（200）包括放大器电路（210），反馈电路（220）和偏置电路（230）。 放大器电路放大从输入端子输入的电压，并将该电压输出到输出端子。 反馈电路连接在输入端子和输出端子之间。 反馈电路包括其总电压值由一个或多个控制信号确定的反馈电阻器部分（221）和并联连接到反馈电阻器部分的反馈晶体管。 偏置电路向反馈晶体管提供预定的偏置电压。
-
Patent Agency Ranking
公开(公告)号：KR1020130059673A
公开(公告)日：2013-06-07
申请号：KR1020110125763
申请日：2011-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/02 , H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A vertical capacitor and a method for forming the same are provided to be manufactured in a substrate without a separate package. CONSTITUTION: An input electrode(14) and an output electrode(15) are formed in the upper surface(10a) of a substrate(10). A conductive material is formed in a first via hole formed by etching the lower surface(10b) of the substrate. The conductive material is connected to the input electrode and the output electrode. An input via electrode(24) and an output via electrode(25) are formed in the substrate. A dielectric layer(37) is formed between the input via electrode and the via electrode.
Abstract translation: 目的：提供垂直电容器及其形成方法，以便在基板上制造而不需要单独的封装。 构成：在基板（10）的上表面（10a）中形成有输入电极（14）和输出电极（15）。 在通过蚀刻基板的下表面（10b）形成的第一通孔中形成导电材料。 导电材料连接到输入电极和输出电极。 在基板中形成有输入通孔电极（24）和输出通孔电极（25）。 在输入通孔电极和通孔电极之间形成介电层（37）。
-
公开(公告)号：KR101208035B1
公开(公告)日：2012-12-05
申请号：KR1020090028546
申请日：2009-04-02
Applicant: 한국전자통신연구원
Abstract: 본발명의실시예에따른전력증폭기의바이어스회로는기준전압을입력받는제 1 입력단, 바이어스제어전압을입력받는제 2 입력단, 상기제 1 입력단과제 1 노드사이에연결된바이어스저항, 상기제 2 입력단과제 2 노드사이에연결되며, 제 1 노드에응답하여전류통로를형성하는제 1 트랜지스터, 상기제 1 노드와제 3 노드사이에연결되며, 상기제 2 노드에응답하여전류통로를형성하는제 2 트랜지스터및 상기제 1 노드와출력단사이에연결되며, 상기출력단을통해바이어스전류를출력하기위한제 3 트랜지스터를포함한다.
-
公开(公告)号：KR1020120071488A
公开(公告)日：2012-07-03
申请号：KR1020100133053
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H01L21/60 , H01L21/306
CPC classification number: H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A fabrication method of backside via holes on a semiconductor substrate is provided to ensure electrical connection from a back side of a substrate to a pad of a front side by uniformly depositing a base metal on a cross section of a via hole. CONSTITUTION: A pad consisting of nickel(102) and gold(103) is formed on a front side of a semiconductor substrate(101). A metal layer is deposited on a back side of the substrate. The deposition of the metal layer is performed by electron-beam deposition, sputtering, or plating. Photoresist having an inclined cross section is applied on the metal layer. The photoresist and the metal layer are simultaneously etched.
Abstract translation: 目的：提供半导体基板上的背面通孔的制造方法，以通过在通孔的横截面上均匀地沉积基底金属来确保从基板的背面到前侧的焊盘之间的电连接。 构成：在半导体衬底（101）的前侧形成由镍（102）和金（103）组成的衬垫。 金属层沉积在基板的背面。 金属层的沉积通过电子束沉积，溅射或电镀进行。 具有倾斜横截面的光刻胶施加在金属层上。 同时蚀刻光致抗蚀剂和金属层。
-
公开(公告)号：KR1020110067929A
公开(公告)日：2011-06-22
申请号：KR1020090124720
申请日：2009-12-15
Applicant: 한국전자통신연구원
CPC classification number: H01F17/0006 , H01F2017/0086 , H01L28/10
Abstract: PURPOSE: An inductor is provided to be mounted on a semiconductor substrate with a small area by using first to fourth vertical conductive units. CONSTITUTION: A first conductive line is electrically connected to a second conductive terminal(140b) and a third conductive terminal(140c). A second conductive line is electrically connected to a first conductive terminal(140a) and a fourth conductive terminal(140d). A third conductive line is electrically connected to the first conductive terminal and the third conductive terminal.
Abstract translation: 目的：通过使用第一至第四垂直导电单元，提供以小面积安装在半导体衬底上的电感器。 构成：第一导电线电连接到第二导电端子（140b）和第三导电端子（140c）。 第二导电线电连接到第一导电端子（140a）和第四导电端子（140d）。 第三导线与第一导电端子和第三导电端子电连接。
-
公开(公告)号：KR1020110024111A
公开(公告)日：2011-03-09
申请号：KR1020090081990
申请日：2009-09-01
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/778 , H01L29/42312 , H01L29/47
Abstract: PURPOSE: A field effect transistor and a manufacturing method thereof are provided to form the field effect transistor of a depletion mode and the field effect transistor of an increase mode on the same substrate by controlling a diffusion depth of the lowermost metal layers. CONSTITUTION: A first gate electrode and a second gate electrode are formed on a Schottky barrier(106). The first gate electrode includes a first lowermost metal layer(120a). The second gate electrode is separated from the first gate electrode and includes a second lowermost metal layer(120b). A first diffusion layer and a second diffusion layer are formed on the first and second lowermost metal layers by thermally processing the substrate.
Abstract translation: 目的：提供一种场效应晶体管及其制造方法，通过控制最下层金属层的扩散深度，在同一基板上形成耗尽型场效应晶体管和增加型场效应晶体管。 构成：在肖特基势垒（106）上形成第一栅电极和第二栅电极。 第一栅电极包括第一最下金属层（120a）。 第二栅电极与第一栅电极分离，并包括第二最下金属层（120b）。 通过热处理基板，在第一和第二最下层金属层上形成第一扩散层和第二扩散层。
-
-
-
-
-
-
-
-
-
Search Results
199
records
(took 0.028 seconds)
