-
公开(公告)号：KR1019980043444A
公开(公告)日：1998-09-05
申请号：KR1019960061302
申请日：1996-12-03
IPC: H01L31/00
Abstract: 본 발명은 반도체 장치의 패키징 및 제작 방법에 관한 것으로써,
전기흡수변조기 모듈 구조 및 그 제작방법에 관한 것으로서,
종래기술에서는 실제 입력신호가 변조기로 전달될 수 있도록 하기 위하여 매우 정교한 패키지의 설계 및 제조 방법이 요구되고, 10Gbps 이상의 초고속의 비트율에서는 설계 및 제조방법에 따라서 그 특성이 크게 좌우되며, 또한, 본딩와이어의 길이에 의해 발생하는 기생 인덕턴스로 인하여 입력신호의 열화를 가져 올 수 있는 문제점이 있었다. 따라서, 본 발명에서는 전송선으로부터 들어온 입력 신호가 전기흡수변조기의 p-측 전극에 도달하게 하고 전기흡수변조기를 통하여 접지로 들어가게 되어있고, 동시에 한쪽이 접지가 된 50Ω 매칭저항에도 연결되어, 전기흡수변조기와 매칭저항이 병렬로 연결되는 구조를 제공함으로써, 와이어본딩을 최소한의 길이로 제한할 수 있고, 또한 동시에 50Ω 매칭이 될 수 있는 것이다.-
公开(公告)号：KR1019980043237A
公开(公告)日：1998-09-05
申请号：KR1019960061030
申请日：1996-12-02
IPC: G02B6/24
Abstract: 본 발명은 단위 광소자용 보조장치에 관한 것으로, 특히, 초소형의 단위 광소자를 광모듈로 조립하기 전에 선행되는 각종 시험과 같은 반복적인 취급 과정을 용이하게 수행할 수 있는 단위 광소자용 보조장치에 관한 것이다.
본 발명에 따른 단위 광소자용 보조장치는, 광소자의 구동시 발생된 열을 분산시키기 위한 받침대(21)와, 받침대(21) 상에 장착되고, 상부에는 전기적인 연결을 위한 적어도 한개의 전극용 금속선(27,28)이 형성되며, 상기한 한개의 전극용 금속선(28)에는 시험용 단위 광소자가 위치하는 탐사침 접점부위(48)가 형성된, 전극용 보조받침대(24)와, 탐사침(46)이 중앙부에 하향으로 삽입 고정되고 그 후방 일측에는 회전봉(42)이 삽입 설치된 회전판(41)과, 상기한 회전봉(42)의 양단을 지지하기 위한 지지대(29,30)와, 상기한 지지대(29,30)와 상기한 전극용 보조받침대(24)를 상기한 받침대(21)에 고정하기 위한 고정수단으로 구성되어, 시험용 단위 광소자의 착탈시에는 상기한 회전판(41)이 회전봉(42)을 중심으로 회동하여 열림 상태로 되는 한편, 시험용 단위 광소자가 상 기한 전극용 보조받침대(24)의 탐사침 접점부위(48) 상에 탑재된 경우에는 상기한 회전판(41)이 회전봉(42)을 중심으로 회동하여 상기한 탐사침(46)이 단위 광소자와 접촉하는 닫힘 상태로 전환되도록 구성된 것을 특징으로 한다.-
公开(公告)号：KR100425583B1
公开(公告)日：2004-04-06
申请号：KR1020010075889
申请日：2001-12-03
Applicant: 한국전자통신연구원
IPC: H04B10/2507 , H04B10/25
Abstract: PURPOSE: A bidirectional dispersion compensator is provided to compensate dispersion of bidirectional optical signals by using the one dispersion compensator, thereby minimizing the number of optical components and reducing size of an entire system. CONSTITUTION: An optical input/output unit(200) inputs and outputs many multiplexed wavelengths. Two ports of the first optical coupler/distributor(210) are connected to the optical input/output unit(200), and the first optical coupler/distributor(210) couples light incident from the two ports, and distributes the coupled light into two lights having the same power, then outputs the lights to other two ports as performing a reverse operation. One port of a phase controller(220) is connected to one of the other ports of the coupler/distributor(210), and the phase controller(220) controls a phase of light incident from the connected port, and performs a reverse operation. One of three ports of the second optical coupler/distributor(230) is connected to the other port of the phase controller(220). The other port of the second optical coupler/distributor(230) is connected to the rest ports of the two ports of the first optical coupler/distributor(210). The second optical coupler/distributor(230) couples light incident from each port, outputs the coupled lights to the rest one port, and performs a reverse operation. A dispersion compensator(240) compensates dispersion of the light incident from the second optical coupler/distributor(230), reflects the compensated light, and outputs the light to the second optical coupler/distributor(230).
Abstract translation: 目的：提供一种双向色散补偿器，以通过使用一个色散补偿器来补偿双向光信号的色散，从而最小化光学组件的数量并减小整个系统的尺寸。 构成：光输入/输出单元（200）输入和输出许多复用波长。 第一光耦合器/分配器（210）的两个端口连接到光输入/输出单元（200），并且第一光耦合器/分配器（210）耦合从两个端口入射的光，并将耦合的光分配到两个 具有相同功率的灯，然后将灯输出到其他两个端口来执行反向操作。 相位控制器（220）的一个端口连接到耦合器/分配器（210）的其他端口之一，并且相位控制器（220）控制从连接的端口入射的光的相位，并执行反向操作。 第二光耦合器/分配器（230）的三个端口之一连接到相位控制器（220）的另一个端口。 第二光耦合器/分配器（230）的另一个端口连接到第一光耦合器/分配器（210）的两个端口的其余端口。 第二光耦合器/分配器（230）耦合从每个端口入射的光，将耦合的光输出到其余的一个端口，并执行反向操作。 色散补偿器（240）补偿从第二光耦合器/分配器（230）入射的光的色散，反射补偿的光并将光输出到第二光耦合器/分配器（230）。
-
公开(公告)号：KR1020030002416A
公开(公告)日：2003-01-09
申请号：KR1020010038011
申请日：2001-06-29
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: PURPOSE: A multi-metal inductor is provided to reduce a loss of a substrate and minimize a loss of a serial resistance generated from an inductor line by controlling the width of metal wires. CONSTITUTION: The first insulating layer(20) of TEOS/BPSG is formed on a silicon substrate(10). The second insulating layer(40) having a structure of SiO2/SOG/SiO2 is formed on the first insulating layer(20). The first metal wire(30) is formed on the second insulating layer(40). A via-hole(50) is formed on the second insulating layer(40) in order to connect the second metal wire(60) for forming the first metal wire(30) and the inductor. The third insulating layer(80) having the structure of SiO2/SOG/SiO2 is formed on the second insulating layer(40). A plurality of metal layers are formed within the third insulating layer(60). The third metal wire(70) is formed on the second metal wire(60). The third metal wire(70) is protected by a protective layer(90). The third metal wire(70) is connected with the second metal wire(60) through a via hole(51).
Abstract translation: 目的：提供多金属电感以减少基板的损耗，并通过控制金属线的宽度来最小化从电感线产生的串联电阻的损失。 构成：TEOS / BPSG的第一绝缘层（20）形成在硅衬底（10）上。 在第一绝缘层（20）上形成具有SiO 2 / SOG / SiO 2结构的第二绝缘层（40）。 第一金属线（30）形成在第二绝缘层（40）上。 为了连接用于形成第一金属线（30）的第二金属线（60）和电感器，在第二绝缘层（40）上形成通孔（50）。 具有SiO 2 / SOG / SiO 2结构的第三绝缘层（80）形成在第二绝缘层（40）上。 在第三绝缘层（60）内形成多个金属层。 第三金属线（70）形成在第二金属线（60）上。 第三金属线（70）由保护层（90）保护。 第三金属线（70）通过通孔（51）与第二金属线（60）连接。
-
公开(公告)号：KR1020020035193A
公开(公告)日：2002-05-11
申请号：KR1020000065358
申请日：2000-11-04
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/7835 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A high frequency power device is provided to simplify a fabricating process, by doping impurities to a trench formed in a source region and by filling polysilicon so that an ion implantation process and a high-temperature diffusion process necessitating high energy become unnecessary. CONSTITUTION: A semiconductor layer is of the first conductivity type. A field region of a trench structure is formed in a side of the semiconductor layer. A gate electrode(44) is formed on a predetermined surface of the semiconductor layer. A channel layer(46) of the second conductivity type is laterally diffused from the field region to a width including both sides of the gate electrode and is formed on the semiconductor layer. A source region(47) of the second conductivity type is formed in the channel layer between one side of the gate electrode and the field region. A drain region(48) of the second conductivity type is formed on the semiconductor layer, having a predetermined interval at the other side of the gate electrode. A sinker(37) of the first conductivity type is connected to the semiconductor layer, having a pillar type of a trench structure which penetrates the source region and forms two source regions. A lightly-doped-drain(LDD) region(45) of the second conductivity type is formed on the semiconductor substrate between the drain region and the gate electrode. The first metal electrode is electrically connected to the semiconductor layer through the sinker, in contact with the source regions. The second metal electrode comes in contact with the drain region.
Abstract translation: 目的：提供高频功率器件，以简化制造工艺，通过将杂质掺杂到在源极区域中形成的沟槽并且通过填充多晶硅，使得不需要离子注入工艺和需要高能量的高温扩散工艺。 构成：半导体层是第一导电类型。 沟槽结构的场区形成在半导体层的一侧。 在半导体层的预定表面上形成栅电极（44）。 第二导电类型的沟道层（46）从场区横向扩散到包括栅电极的两侧的宽度，并形成在半导体层上。 在栅电极的一侧和场区之间的沟道层中形成第二导电类型的源极区（47）。 第二导电类型的漏区（48）形成在半导体层上，在栅电极的另一侧具有预定间隔。 第一导电类型的沉降片（37）连接到具有贯穿源极区域并形成两个源极区域的沟槽结构的柱状的半导体层。 在漏区和栅电极之间的半导体衬底上形成第二导电类型的轻掺杂漏极（LDD）区（45）。 第一金属电极通过沉降片与半导体层电连接，与源极区域接触。 第二金属电极与漏极区域接触。
-
Patent Agency Ranking
公开(公告)号：KR1020010076771A
公开(公告)日：2001-08-16
申请号：KR1020000004126
申请日：2000-01-28
Applicant: 한국전자통신연구원
IPC: G02B6/30
Abstract: PURPOSE: An optical subassembly having a plastic receptacle for receiving silicon optical bench is provided to easily combine an optical element equipped on a surface of a silicon substrate with an optical ferrule. CONSTITUTION: A silicon substrate(25) is inserted into a receptacle through inserting holes and placed on a predetermined position. Here, the silicon substrate(25) can move to x-direction or y-direction, since a distance and height between two inserting holes are designed to be bigger at least several micro-meters than a width and thickness of each silicon substrate(25). Accordingly, an error caused by cutting the silicon substrate(25) and a misalignment between aligning devices, of a surface of the silicon substrate and the silicon substrate of the receptacle, are removed, respectively.
Abstract translation: 目的：提供一种具有用于接收硅光学台的塑料插座的光学子组件，以容易地将装配在硅衬底的表面上的光学元件与光学套圈组合。 构成：通过插入孔将硅衬底（25）插入插座并放置在预定位置。 这里，由于两个插入孔之间的距离和高度被设计为比每个硅衬底（25）的宽度和厚度至少几微米，所以硅衬底（25）可以移动到x方向或y方向 ）。 因此，分别去除了硅衬底（25）的切割和硅衬底的表面和插座的硅衬底的对准装置之间的未对准引起的误差。
-
公开(公告)号：KR1020010010805A
公开(公告)日：2001-02-15
申请号：KR1019990029887
申请日：1999-07-23
Applicant: 한국전자통신연구원
IPC: G02B6/36
Abstract: PURPOSE: An optical subassembly and a fabrication method thereof are provided to achieve the optical subassembly of small size, to simplify the coupling between an optical fiber and an optical device, and to reducing the production cost. CONSTITUTION: An optical module consists of a mold housing(11), a silicon optical bench(12), a bedplate(13), and a printed circuit board(14). The mold housing is aligned with the silicon bench by inserting a guide plate(25,26) of the mold housing into a guide groove(18,15) of the silicon bench. A case(22) of the mold housing and the printed circuit board is sealed with epoxy. An optical fiber(28) is inserted in a crenated gap(17) of a V-shaped groove(16) of the silicon optical bench via an optical fiber inserting opening(29) and the guide groove. The optical fiber is compressed by a push plate(24) of the mold housing, thereby being tightly contacted in the V-shaped groove. Therefore, the optical fiber is aligned by only the V-shaped groove of the silicon bench. The inserted optical fiber is firmly fixed by sealing the optical fiber inserting opening with epoxy. In the hand alignment method of the optical device and the optical fiber using the silicon optical bench, a die bonding pad or a flip chip bonding pad is used for attaching the optical device, an alignment mark is used as a mate alignment means relative to the V-shaped groove.
Abstract translation: 目的：提供一种光学组件及其制造方法，以实现小尺寸的光学组件，以简化光纤和光学器件之间的耦合，并降低生产成本。 构成：光学模块由模具壳体（11），硅光学台（12），底板（13）和印刷电路板（14）组成。 通过将模具壳体的引导板（25,26）插入硅工作台的引导槽（18,15）中，将模具壳体与硅台架对准。 模具外壳和印刷电路板的外壳（22）用环氧树脂密封。 光纤（28）经由光纤插入口（29）和引导槽插入到硅光学平台的V形槽（16）的楔形间隙（17）中。 光纤被模具壳体的推板（24）压缩，从而在V形槽中紧密接触。 因此，仅通过硅台架的V形槽对准光纤。 插入的光纤通过用环氧树脂密封光纤插入口牢固地固定。 在光学装置的手对准方法和使用硅光学台的光纤中，使用芯片接合焊盘或倒装芯片焊盘来安装光学装置，使用对准标记作为对准装置 V形槽。
-
公开(公告)号：KR100261297B1
公开(公告)日：2000-07-01
申请号：KR1019970054785
申请日：1997-10-24
IPC: G02B6/00
Abstract: PURPOSE: An optical fiber having a grating formed at its end and a method of fabricating the optical fiber are provided, which is constructed in a manner that a diffraction grating or reflection grating is formed at the end of the optical fiber to focus, collimate, split, antireflect, polarize and filter beams. CONSTITUTION: A master grating pattern(60) that will be transferred to an optical fiber(50) is formed on a silicon master substrate. The optical fiber and the master substrate are heated and pressed to transfer the grating from the master surface of the substrate to the section(51) of the optical fiber, to thereby fabricate an optical fiber having the grating formed at its end.
Abstract translation: 目的：提供一种在其端部形成有光栅的光纤和制造光纤的方法，其以在光纤端部形成衍射光栅或反射光栅来聚焦，准直， 分裂，抗反射，极化和滤光片。 构成：将在硅母板上形成将被转移到光纤（50）的主光栅图案（60）。 对光纤和母板进行加热和压制，以将光栅从基片的主表面转移到光纤的部分（51），从而制造在其端部形成有光栅的光纤。
-
公开(公告)号：KR1020000024926A
公开(公告)日：2000-05-06
申请号：KR1019980041730
申请日：1998-10-02
IPC: G01R15/00
Abstract: PURPOSE: A circuit for distinguishing reliabilities of photo diodes is provided to secure the reliability of photo diodes while minimizing expenses and time of a reliability screening process by distinguishing light emitting diodes as good or bad with turn-on and turn-off states. CONSTITUTION: A resistor(2) is used to control an electric current. A photo diode is grounded in a reverse direction. A trnasistor(4) for amplifying current and rheostat(5) connected with a base are connected to one end of the photo diode(3) to detect changes of the electric current. A rheostat(6) connected with an emitter is connected to the other end of the phote diode to adjust a reliability distinguishment reference with a signal of the trnasistor and the rheostat(4,5) and a logic stage voltage from external. Two NOR gates(7,8) output a control signal for distinguishing photo diodes as good or bad. A red LED and green LED(9,10) display the good and bad states of the photo diodes.
Abstract translation: 目的：提供用于区分光电二极管的可靠性的电路，以确保光二极管的可靠性，同时通过将发光二极管区分为导通和关断状态的好坏来最小化可靠性筛选过程的费用和时间。 构成：电阻（2）用于控制电流。 光电二极管反向接地。 用于放大与基极连接的电流和变阻器（5）的三极管（4）连接到光电二极管（3）的一端以检测电流的变化。 与发射极连接的变阻器（6）连接到光电二极管的另一端，以通过trnasistor和变阻器（4,5）的信号和来自外部的逻辑级电压来调节可靠性鉴别参考。 两个NOR门（7,8）输出用于区分光电二极管的控制信号是好还是坏。 红色LED和绿色LED（9,10）显示光电二极管的良好和坏状态。
-
公开(公告)号：KR1020000019557A
公开(公告)日：2000-04-15
申请号：KR1019980037714
申请日：1998-09-12
Applicant: 한국전자통신연구원
CPC classification number: G02B6/423 , G02B6/136 , G02B6/30 , G02B6/42 , G02B6/4201 , G02B6/4214 , G02B6/4224 , G02B6/4232 , G02B6/4243 , H01L31/02325
Abstract: PURPOSE: A method for fabricating a substrate for a hybrid optical integrated circuit is provided to minimize a picture transcription alignment error between a rib region, an alignment mark and V-groove pattern. CONSTITUTION: A method for fabricating a substrate for a hybrid optical integrated circuit comprises the steps of: selectively etching a crystalline silicon layer of an SOI wafer composed of a silicon substrate, a buried insulating film and the crystalline silicon layer to form an SOI slap(55); forming an LPCVD silicon nitride film(57) and an etch protecting film at an upper part of an overall structure of the SOI wafer; selectively etching the etch protecting film and the LPCVD silicon nitride film so as to expose the crystalline silicon of the SOI slap except a rib region and forming marks(62) for an optical device alignment and a V-groove etch window for an optical fiber alignment; selectively etching the crystalline silicon layer exposed at the upper part of the SOI slap to form an SOI rib; selectively removing the etch protecting film of the upper part of the SOI slap and the LPCVD silicon nitride film; forming a cladding layer(81) of an optical wave guide at a surface of the SOI slap comprising the SOI rib; an isotropically etching the silicon substrate exposed at the V-groove etch window to form a V-groove for an optical fiber alignment; and selectively removing the etch protecting film of a region adjacent to both ends of the SOI slap to expose the LPCVD silicon nitride film.
Abstract translation: 目的：提供一种制造用于混合光集成电路的衬底的方法，以最小化肋区域，对准标记和V形槽图案之间的图像转录对准误差。 构成：用于制造用于混合光集成电路的衬底的方法包括以下步骤：选择性地蚀刻由硅衬底，埋入绝缘膜和晶体硅层组成的SOI晶片的晶体硅层，以形成SOI片（ 55）; 在SOI晶片的整个结构的上部形成LPCVD氮化硅膜（57）和蚀刻保护膜; 选择性地蚀刻蚀刻保护膜和LPCVD氮化硅膜，以暴露除了肋区域之外的SOI照射的晶体硅，并形成光学器件对准的标记（62）和用于光纤对准的V沟槽蚀刻窗口 ; 选择性地蚀刻在SOI拍打的上部暴露的晶体硅层以形成SOI肋; 选择性地去除SOI薄片的上部的蚀刻保护膜和LPCVD氮化硅膜; 在包括所述SOI肋的所述SOI电击的表面处形成光波导的包覆层（81）; 各向同性蚀刻在V槽蚀刻窗处暴露的硅衬底，以形成用于光纤对准的V形槽; 并且选择性地去除与SOI拍打的两端相邻的区域的蚀刻保护膜，以暴露LPCVD氮化硅膜。
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.024 seconds)
