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    Techniques for providing option conductors to connect components in oscillator circuit
    51.
    发明专利
    Techniques for providing option conductors to connect components in oscillator circuit 有权
    提供选择导体连接振荡器电路中组件的技术

    公开(公告)号：JP2013102456A

    公开(公告)日：2013-05-23

    申请号：JP2012275471

    申请日：2012-12-18

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ALI ATESOGLU

    IPC: H03B5/08 ,  H03B5/12 ,  H03L7/099

    CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

    Abstract: PROBLEM TO BE SOLVED: To provide techniques which allow use of option conductors to connect components in an oscillator circuit.SOLUTION: An oscillator circuit 200 includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes varactors 203 to 206, capacitors 221 to 226, and option conductors 207, 208, and 212 to 216 in a second conductive layer. The option conductors each form at least a portion of a connection between one of the transistors and one of a capacitor and a varactor. The oscillator circuit may further include an inductor coupled to one of a plurality of first transistors through the routing conductors in the first conductive layer, and a second option conductor in the second conductive layer that forms a first portion of the inductor.

    Abstract translation: 要解决的问题：提供允许使用选项导体连接振荡器电路中的组件的技术。 解决方案：振荡器电路200包括通过第一导电层中的布线导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的可变电抗器203至206，电容器221至226以及选项导体207,208和212至216。 选项导体各自形成晶体管之一和电容器和变容二极管之一之间的连接的至少一部分。 振荡器电路还可以包括通过第一导电层中的路由导体耦合到多个第一晶体管中的一个的电感器，以及形成电感器的第一部分的第二导电层中的第二选择导体。 版权所有（C）2013，JPO＆INPIT

    Digital adaptation circuit network and method for programmable logic device
    52.
    发明专利
    Digital adaptation circuit network and method for programmable logic device 审中-公开
    数字适配​​电路和可编程逻辑器件的方法

    公开(公告)号：JP2011193505A

    公开(公告)日：2011-09-29

    申请号：JP2011100172

    申请日：2011-04-27

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

    IPC: H04L25/03 ,  H04B3/06

    CPC classification number: H04L25/03885

    Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuit network and a method for a programmable logic device.
    SOLUTION: The method controls the equalization of an incoming data signal. The method includes steps for: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供数字适配电路网络和可编程逻辑器件的方法。

    解决方案：该方法控制输入数据信号的均衡。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT

    Heterogeneous transceiver architecture for wide-range programmability of programmable logic
    53.
    发明专利
    Heterogeneous transceiver architecture for wide-range programmability of programmable logic 有权
    用于可编程逻辑的宽范围可编程性的异构收发器架构

    公开(公告)号：JP2007282183A

    公开(公告)日：2007-10-25

    申请号：JP2006351009

    申请日：2006-12-27

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SHUMARAYEV SERGEY ,  BEREZA BILL W ,  LEE CHONG H ,  RAKESH PATEL H ,  WONG WILSON

    IPC: H03K19/173

    CPC classification number: H04L5/14 ,  H03K19/17744 ,  H04L27/00

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic device ("PLD") that can support over a wide range of assumed serial data communication speeds (including 10 to 12 Gbps).
    SOLUTION: A high-speed serial data transceiver network on a programmable logic device ("PLD") includes some channels that are able to operate at data rates, up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates, up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase-locked loop ("PLL") network, and have other circuit components that are typically needed for handling the data that are transmitted at relatively low data rates. The relatively high-speed channels are served by a relatively high-speed PLL network, and have other circuit components that are typically needed for handling data that are transmitted at relatively high data rates.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供可支持广泛范围的假设串行数据通信速度（包括10到12 Gbps）的可编程逻辑器件（“PLD”）。 解决方案：可编程逻辑器件（“PLD”）上的高速串行数据收发器网络包括一些能够以数据速率操作的通道，最多可达到第一个相对较低的最大数据速率，以及其他通道 能够以高达第二，相对较高的最大数据速率的数据速率进行操作。 相对低速的通道由相对低速的锁相环（“PLL”）网络服务，并且具有处理以相对低的数据速率传输的数据通常需要的其他电路部件。 相对高速的信道由相对高速的PLL网络服务，并且具有通常用于处理以相对高的数据速率发送的数据所需的其他电路部件。 版权所有（C）2008，JPO＆INPIT

    Wide range and dynamically reconfigurable clock data recovery architecture
    54.
    发明专利
    Wide range and dynamically reconfigurable clock data recovery architecture 审中-公开
    宽范围和动态可重构时钟数据恢复架构

    公开(公告)号：JP2007043717A

    公开(公告)日：2007-02-15

    申请号：JP2006211486

    申请日：2006-08-02

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： HOANG TIM T ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  RAKESH PATEL H

    IPC: H03L7/08 ,  H03K5/00 ,  H04L7/033

    CPC classification number: H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

    Abstract: PROBLEM TO BE SOLVED: To provide a CDR architecture operable over a wide range of data rates. SOLUTION: A wide range and dynamically reconfigurable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammable without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供可在宽范围的数据速率下操作的CDR架构。 解决方案：宽范围和动态可重配置的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 这些参数可以动态重新编程，而不会关闭电路或PLD。 这允许CDR电路在各种标准和协议之间进行即时切换。 版权所有（C）2007，JPO＆INPIT

    Interconnection and input/output resources for programmable logic integrated circuit device
    55.
    发明专利
    Interconnection and input/output resources for programmable logic integrated circuit device 有权
    可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：JP2006246534A

    公开(公告)日：2006-09-14

    申请号：JP2006146010

    申请日：2006-05-25

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection resource for applying to a programmable logic device for increasing the operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of programmable logic regions (20), disposed on the device with a plurality of intersecting the rows and columns of such regions. Interconnection resources for making programmable interconnections to, from and/or between the regions (e.g., interconnecting conductors or the like) are provided on the device. At least some of these interconnection resources are constituted of two forms, that are architecturally similar but that have markedly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what is called a "normal signal speed", while the smaller of the portions (200b, 210b, 230b) has a significantly higher signal speed. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供用于应用于可编程逻辑器件的互连资源，以提高可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域（20）设置在多个与这些区域的行和列相交的装置上。 用于在区域之间（或连接导体等）进行可编程互连的互连资源设置在该设备上。 这些互连资源中的至少一些由架构上相似但具有明显不同的信号传播速度特性的两种形式构成。 例如，这种双形互连资源（200a，210a，230a）的主要或较大部分可以具有所谓的“正常信号速度”，而较小的部分（200b，210b，230b）具有显着的 信号速度更高。 版权所有（C）2006，JPO＆NCIPI

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