公开(公告)号：DE69423938D1

公开(公告)日：2000-05-18

申请号：DE69423938

申请日：1994-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  GREGOIRE DENNIS GERARD ,  YOUNGS AMY MAY

IPC: G06F12/08

Abstract: A data processing system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device 20, 22 which is writing to a device 7 on the system bus 5 asynchronously when compared to the CPU clock 1. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

公开(公告)号：SG71192A1

公开(公告)日：2000-03-21

申请号：SG1999000590

申请日：1999-02-13

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN

IPC: G06F12/08

Abstract: A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which denote the same coherency information as the shared state plus additional information regarding the contents/coherency of the subject cache entry. One substate, SIC0, indicates that the cache entry is assumed to contain instructions since the contents were retrieved from system memory as a result of an instruction fetch operation. The second substate, SIC1, indicates the same information plus that a snooped flush operation hit the subject cache entry while its coherency was in the first shared substate. Deallocation of a cache entry in the first substate of the shared coherency state within lower level (e.g., L3) caches does not result in the contents of the same cache entry in an L2 cache being invalidated. Once the first substate is entered, the coherency state does not transition to the invalid state unless an operation designed to invalidate instructions is received. Operations from a local processor which contravene the presumption that the contents comprise instructions may cause the coherency state to transition to an ordinary shared state. Since the contents of a cache entry in the two coherency substates are presumed to be instructions, not data, instructions within an L2 cache are not discarded as a result of snooped flushes, but are retained for possible reloads by a local processor.

公开(公告)号：DE69023677D1

公开(公告)日：1996-01-04

申请号：DE69023677

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

公开(公告)号：MY122483A

公开(公告)日：2006-04-29

申请号：MYPI9900163

申请日：1999-01-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A FIRST DATA ITEM IS STORED IN A FIRST CACHE (14A -14N) IN ASSOCIATION WITH AN ADDRESS TAG (40) INDICATING AN ADDRESS OF THE DATA ITEM. A COHERENCY INDICATOR (42) IN THE FIRST CACHE IS SET TO A FIRST STATE (82) THAT INDICATES THAT THE FIRST DATA ITEM IS VALID. IN RESPONSE TO ANOTHER CACHE INDICATING AN INTENT TO STORE TO THE ADDRESS INDICATED BY THE ADDRESS TAG WHILE THE COHERENCY INDICATOR IS SET TO THE FIRST STATE, THE COHERENCY INDICATOR IS UPDATED TO A SECOND STATE (90) THAT INDICATES THAT THE ADDRESS TAG IS VALID AND THAT THE FIRST DATA ITEM IS INVALID. THEREAFTER, IN RESPONSE TO DETECTION OF A REMOTELY SOURCED DATA TRANSFER THAT IS ASSOCIATED WITH THE ADDRESS INDICATED BY THE ADDRESS TAG AND THAT INCLUDES A SECOND DATA ITEM, A DETERMINATION IS MADE, IN RESPONSE TO A MODE OF OPERATION OF THE FIRST CACHE, WHETHER OR NOT TO UPDATE THE FIRST CACHE. IN RESPONSE TO A DETERMINATION TO MAKE AN UPDATE TO THE FIRST CACHE, THE FIRST DATA ITEM IS REPLACED BY STORING THE SECOND DATA ITEM IN ASSOCIATION WITH THE ADDRESS TAG AND THE COHERENCY INDICATOR IS UPDATED TO A THIRD STATE (84) THAT INDICATES THAT THE SECOND DATA ITEM IS VALID. IN ONE EMBODIMENT, THE OPERATING MODES OF THE FIRST CACHE INCLUDE A PRECISE MODE IN WHICH CACHE UPDATES ARE ALWAYS PERFORMED AND AN IMPRECISE MODE IN WHICH CACHE UPDATES ARE SELECTIVELY PERFORMED. THE OPERATING MODE OF THE FIRST CACHE MAY BE SET BY EITHER HARDWARE OR SOFTWARE.

公开(公告)号：MY119935A

公开(公告)日：2005-08-30

申请号：MYPI9900183

申请日：1999-01-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN

IPC: G06F12/14 ,  G06F12/08 ,  G06F12/12

Abstract: A MODIFIED MESI CACHE COHERENCY PROTOCOL IS IMPLEMENTED WITHIN A LEVEL TWO (L2) CACHE ACCESSIBLE TO A PROCESSOR HAVING BIFURCATED LEVEL ONE (LL) DATA AND INSTRUCTION CACHES. THE MODIFIED MESI PROTOCOL INCLUDES TWO SUBSTATES OF THE SHARED STATE, WHICH DENOTE THE SAME COHERENCY INFORMATION AS THE SHARED STATE PLUS ADDITIONAL INFORMATION REGARDING THE ONTENTS/COHERENCY OF THE SUBJECT CACHE ENTRY. ONE SUBSTATE, SIC0, INDICATES THAT THE CACHE ENTRY IS ASSUMED TO CONTAIN INSTRUCTIONS SINCE THE CONTENTS WERE RETRIEVED FROM SYSTEM MEMORY AS A RESULT OF AN INSTRUCTION FETCH OPERATION. THE SECOND SUBSTATE, SIC1, INDICATES THE SAME INFORMATION PLUS THAT A SNOOPED FLUSH OPERATION HIT THE SUBJECT CACHE ENTRY WHILE ITS COHERENCY WAS IN THE FIRST SHARED SUBSTATE. DEALLOCATION OF A CACHE ENTRY IN THE FIRST SUBSTATE OF THE SHARED COHERENCY STATE WITHIN LOWER LEVEL (E.G., L3) CACHES DOES NOT RESULT IN THE CONTENTS OF THE SAME CACHE ENTRY IN AN L2 CACHE BEING INVALIDATED. ONCE THE FIRST SUBSTATE IS ENTERED, THE COHERENCY STATE DOES NOT TRANSITION TO THE INVALID STATE UNLESS AN OPERATION DESIGNED TO INVALIDATE INSTRUCTIONS IS RECEIVED. OPERATIONS FROM A LOCAL PROCESSOR WHICH CONTRAVENE THE PRESUMPTION THAT THE CONTENTS COMPRISE INSTRUCTIONS MAY CAUSE THE COHERENCY STATE TO TRANSITION TO AN ORDINARY SHARED STATE. SINCE THE CONTENTS OF A CACHE ENTRY IN THE TWO COHERENCY SUBSTATES ARE PRESUMED TO BE INSTRUCTIONS, NOT DATA, INSTRUCTIONS WITHIN AN L2 CACHE ARE NOT DISCARDED AS A RESULT OF SNOOPED FLUSHES, BUT ARE RETAINED FOR POSSIBLE RELOADS BY A LOCAL PROCESSOR.

公开(公告)号：AU2003298240A8

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  STARKE WILLIAM JOHN ,  CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：DE69529381D1

公开(公告)日：2003-02-20

申请号：DE69529381

申请日：1995-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  KAISER JOHN MICHAEL

IPC: G06F13/362 ,  G06F15/16 ,  G06F13/364 ,  G06F15/177

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

公开(公告)号：RU2183850C2

公开(公告)日：2002-06-20

申请号：RU99123716

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON DZHON STIVEN ,  KEJZER DZHON MAJKL ,  LUIS DZHERRI DON

IPC: G06F12/08 ,  G06F12/0831

Abstract: computer engineering. SUBSTANCE: invention specifically refers to performance of reading operations from storage of symmetric multiprocessor computer systems. It is suggested in accordance with method that after loading of information at least two caches of system storage should be marked as those containing joint, invariable copies of information. When interrogating processor sends message showing that it wants to read information one certain cache generates reply which indicates that it is information source. This reply is transferred to cache extracting message from circuit of internal connections that is linked to interrogating processor. Reply is detected by system logic and is directed from it into interrogating processor. Then cache generates information into circuit of internal connections which is connected to interrogating processor. System storage detects message and as rule acts as information source. But reply in this case informs storage of system on fact that cache is information source instead of storage. Since delay in cache storage can be shorter than in system storage then employment of such new protocol enables reading efficiency to be substantially improved. EFFECT: development of improved method of reading operations in multiprocessor computer system. 34 cl, 3 dwg

公开(公告)号：AT191803T

公开(公告)日：2000-04-15

申请号：AT94306613

申请日：1994-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  GREGOIRE DENNIS GERARD ,  YOUNGS AMY MAY

IPC: G06F12/08

Abstract: A data processing system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device 20, 22 which is writing to a device 7 on the system bus 5 asynchronously when compared to the CPU clock 1. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

公开(公告)号：PL331475A1

公开(公告)日：1999-08-30

申请号：PL33147599

申请日：1999-02-16

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/00 ,  G06F12/08 ,  G06F7/00 ,  G11B5/012

Abstract: In evicting data from a first cache in a level other than the lowest in a multilevel cache hierarchy, data is written to the system bus and snooped back into a second cache on a lower level in the cache hierarchy. The need for a private data path between the two caches is thus eliminated, and the second cache memory need not be dual-ported. The reload path employed for updating the second cache is reused to snoop cast-outs off the system bus. As a result of the first cache evicting data via the system bus, the second cache never contains data which is modified (M) with respect to system memory and other devices in a multiprocessor system get updated earlier. The need for error correction code (ECC) checking is eliminated, together with the associated additional bits, and may be replaced by simple parity checking. The bus into the second cache thus requires fewer bits, consumes less area, and may be operated at a higher frequency. When employed in conjunction with an H-MESI cache coherency protocol, horizontal devices go from the hovering (H) state to the shared (S) state faster.