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    METHOD FOR CREATING EXTREMELY SHALLOW SOURCE/DRAIN EXPANSION PART BY DOPING GATE AND SEMICONDUCTOR RESULTING THEREFROM
    53.
    发明专利
    METHOD FOR CREATING EXTREMELY SHALLOW SOURCE/DRAIN EXPANSION PART BY DOPING GATE AND SEMICONDUCTOR RESULTING THEREFROM 失效

    公开(公告)号：JP2000036596A

    公开(公告)日：2000-02-02

    申请号：JP11771499

    申请日：1999-04-26

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  STEPHEN J HOLMES ,  DAVID V HORAK

    IPC: H01L29/78 ,  H01L21/223 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To form a narrow gate and a shallow expansion part by providing a layer (substrate) including one polysilicon gate and one source/drain region, and by simultaneously doping one gate stack and the source/drain region. SOLUTION: Vapor-phase doping is selectively used, and a polysilicon gate and an S/D region are simultaneously doped. Especially, a gate stack 20 and a well 18 that are not doped are covered with an appropriate diffusion prevention material 40. An S/D region 19 and a polysilicon gate 24 are exposed to n- and p-type gases or a doping source 30 of plasma. The gases can be variously changed corresponding to p and n types. For example, arsine AsH3 is used as arsenic trichloride AsCl3, phosphine PH3, and n-type gas dopant. When a masked laser beam is used, a diffusion prevention material 40 is eliminated, and reaction is repeated for the remaining stack 20 and the S/D region 19 by a type opposite to the doping source being used firstly.

    Method of forming semiconductor structure
    54.
    发明专利
    Method of forming semiconductor structure 有权
    形成半导体结构的方法

    公开(公告)号：JP2013201449A

    公开(公告)日：2013-10-03

    申请号：JP2013115224

    申请日：2013-05-31

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  JOHN GERARD GAUDIELLO ,  HACKNEY MARC CHARLES ,  STEVEN JOHN HOLMES ,  DAVID VACLAV HORAK ,  CHARLES WILLIAM KOBURGER III ,  JACK ALLAN MANDELMAN ,  WILLIAM ROBERT TONTI

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

    CPC classification number: H01L21/76264

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a semiconductor structure.SOLUTION: The method comprises the steps of: bonding a first dielectric layer on a first semiconductor layer with a second dielectric layer on a second semiconductor layer; defining a plurality of openings extending from a top surface of the first semiconductor layer to the second semiconductor layer; applying dielectric regions to sidewalls of each of the openings; epitaxially growing an island of semiconductor material of the second semiconductor layer to fill each of the openings; forming an insulating layer at a given depth that divides the first semiconductor layer into a plurality of device regions between the insulating layer and the top surface and a plurality of body regions between the insulating layer and the first and second dielectric layers such that each of the body regions is aligned with one of the device regions between an adjacent pair of the dielectric regions; forming shallow trench isolation regions extending from the top surface of the first semiconductor layer; and forming a contact through each of the shallow trench isolation regions to the body regions.

    Abstract translation: 要解决的问题：提供一种形成半导体结构的方法。解决方案：该方法包括以下步骤：在第二半导体层上将第一介电层与第二介电层接合在第一半导体层上; 限定从所述第一半导体层的顶表面延伸到所述第二半导体层的多个开口; 将介质区域施加到每个开口的侧壁; 外延生长第二半导体层的半导体材料岛以填充每个开口; 在给定的深度处形成绝缘层，所述绝缘层将所述第一半导体层划分成所述绝缘层和所述顶表面之间的多个器件区域以及所述绝缘层与所述第一和第二电介质层之间的多个体区域，使得 身体区域与相邻的一对电介质区域之间的器件区域之一对准; 形成从第一半导体层的顶表面延伸的浅沟槽隔离区; 以及通过每个浅沟槽隔离区域形成到身体区域的接触。

    Method and equipment for immersion lithography
    56.
    发明专利
    Method and equipment for immersion lithography 审中-公开
    渗透层析的方法和设备

    公开(公告)号：JP2006148092A

    公开(公告)日：2006-06-08

    申请号：JP2005319158

    申请日：2005-11-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  MARK C HEIKY ,  CORLISS DANIEL A ,  DAVID V HOLLACK ,  KOBURGER CHARLES W

    IPC: H01L21/027 ,  G03F7/20 ,  H01L21/683

    CPC classification number: G03F7/707 ,  G03F7/70341 ,  G03F7/70808

    Abstract: PROBLEM TO BE SOLVED: To provide a method and equipment in which the possibility of bringing immersion fluid from a clearance or other portion of a chuck onto the surface of a photoresist layer on a wafer is not high. SOLUTION: Equipment for holding a wafer and a method for immersion lithography. The equipment comprises a wafer chuck having a central circular vacuum platen, an outside region, and a circular groove centering on the vacuum platen. Upper surface of the vacuum platen is recessed below the upper surface of the outside region, and the layer surface of the groove is recessed below the upper part of the vacuum platen, one or more suction ports are provided in the lower surface of the groove, and a hollow toroidal bladder capable of expansion or contraction is arranged in the groove. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种方法和设备，其中将来自夹盘的间隙或其他部分的浸没流体的可能性提供到晶片上的光致抗蚀剂层的表面上的可能性不高。

    解决方案：用于保持晶片的设备和浸没式光刻方法。 该设备包括具有中心圆形真空压板，外部区域和以真空压板为中心的圆形槽的晶片卡盘。 真空压板的上表面在外部区域的上表面下方凹陷，并且凹槽的表面凹陷在真空压板的上部下方，在凹槽的下表面中设置一个或多个吸入口， 并且在槽中布置能够膨胀或收缩的空心环形囊。 版权所有（C）2006，JPO＆NCIPI

    Semiconductor structure and method of manufacturing semiconductor (semiconductor optical sensor)
    57.
    发明专利
    Semiconductor structure and method of manufacturing semiconductor (semiconductor optical sensor) 有权
    半导体结构及制造半导体光电传感器的方法

    公开(公告)号：JP2007142416A

    公开(公告)日：2007-06-07

    申请号：JP2006308607

    申请日：2006-11-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KOBURGER CHARLES W III ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  DAVID VACLAV HORAK

    IPC: H01L31/02

    CPC classification number: H01L31/101 ,  H01L27/14647 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor and a method of forming the optical sensor.
    SOLUTION: The optical sensor structure includes (a) a semiconductor substrate, (b) a first, a second, a third, a fourth, a fifth, and a sixth electrodes and (c) a first, a second, and a third semiconductor regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is deeper than the second depth, and the second depth is deeper than the third depth. The first semiconductor region, the second semiconductor region, and the third semiconductor region are laid out between the first electrode and the fourth electrode, between the second electrode and the fifth electrode, and between the third electrode and the sixth electrodes, respectively, and are in contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first semiconductor region, the second semiconductor region, and the third semiconductor region come into contact with each other.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种光学传感器和形成光学传感器的方法。 解决方案：光学传感器结构包括（a）半导体衬底，（b）第一，第二，第三，第四，第五和第六电极和（c）第一，第二和第 第三半导体区域。 第一和第四电极处于第一深度。 第二和第五电极处于第二深度。 第三和第六电极处于第三深度。 第一深度比第二深度深，第二深度比第三深度深。 第一半导体区域，第二半导体区域和第三半导体区域分别布置在第一电极和第四电极之间，第二电极和第五电极之间以及第三电极和第六电极之间，并且分别是 分别与第一和第四电极，第二和第五电极以及第三和第六电极接触。 第一半导体区域，第二半导体区域和第三半导体区域彼此接触。 版权所有（C）2007，JPO＆INPIT

    Wrap-around type gate field effect transistor
    60.
    发明专利
    Wrap-around type gate field effect transistor 有权
    缠绕型门控场效应晶体管

    公开(公告)号：JP2005175485A

    公开(公告)日：2005-06-30

    申请号：JP2004353618

    申请日：2004-12-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    Abstract: PROBLEM TO BE SOLVED: To provide a gate formation method capable of controlling the gate length of a self-aligned wrap-around type field effect transistor easily, accurately, and securely. SOLUTION: A reference edge in the vertical direction is determined by forming a cavity in an silicon on insulator (SOI) structure having an embedded silicon island 108. In order to securely carry out an etch back, the reference edge is used in two etch back stages. In the first etch back, part of oxide layer corresponding to a first distance is removed and then, a gate conductive material is applied thereon. In the second etch back, part of the gate conductive material corresponding to a second distance is removed. The difference between the first distance and the second distance determines the final gate length of a device. After the oxide layer is peeled off and removed, gate electrodes 904 and 906 in the vertical direction surrounding the embedded silicon island 108 appear at all four sides. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够容易，准确且可靠地控制自对置环绕型场效应晶体管的栅极长度的栅极形成方法。 解决方案：通过在具有嵌入硅岛108的绝缘体上硅（SOI）结构中形成空腔来确定垂直方向上的参考边缘。为了可靠地执行回蚀刻，参考边缘用于 两个回蚀阶段。 在第一回蚀刻中，除去对应于第一距离的部分氧化物层，然后在其上施加栅极导电材料。 在第二次回蚀时，去除对应于第二距离的栅极导电材料的一部分。 第一距离和第二距离之间的差值决定了装置的最终栅极长度。 在去除和除去氧化物层之后，围绕嵌入硅岛108的垂直方向的栅电极904和906出现在所有四个侧面。 版权所有（C）2005，JPO＆NCIPI

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