公开(公告)号：DE59902603D1

公开(公告)日：2002-10-10

申请号：DE59902603

申请日：1999-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MAJDIC ANDREJ

IPC: G11C29/04 ,  G06F11/20 ,  G11C29/00

Abstract: An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.

公开(公告)号：DE59901953D1

公开(公告)日：2002-08-08

申请号：DE59901953

申请日：1999-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS ,  KOWARIK OSKAR ,  HOFFMANN KURT

IPC: G11C11/22 ,  G11C29/12

Abstract: A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

公开(公告)号：DE10061580A1

公开(公告)日：2002-06-27

申请号：DE10061580

申请日：2000-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C8/02 ,  G11C11/15 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: The aim of the invention is to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate conduction device (50) of a memory device (1) which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor (10) and hence, the information that is stored.

公开(公告)号：DE10057806A1

公开(公告)日：2002-06-06

申请号：DE10057806

申请日：2000-11-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  DEHM CHRISTINE

IPC: H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: The contact plugs (26) to the top capacitor electrodes of each memory cell are not manufactured from below but from above. First the capacitor formed by the upper (22) and lower (24,24s) capacitor electrodes and the dielectric (23) are manufactured. A hole for the contact plug to the top electrode is then etched through the top electrode and the dielectric and filled with a conductive material to connect top electrode with the substrate.

公开(公告)号：DE10056159A1

公开(公告)日：2002-05-23

申请号：DE10056159

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  G11C11/14 ,  G11C11/02

Abstract: The memory device has a matrix of magnetic tunnel junction memory cells (1), each connected between a bit line (B1-B4) and a plate line (PL), with selection transistors coupled to the plate line connected at their gate electrodes to perpendicular word lines (W1-W4). Each selection transistor is associated with several magnetic tunnel junction memory cells, with its channel width determined by the number of associated magnetic tunnel junction memory cells.

公开(公告)号：DE10042222A1

公开(公告)日：2002-03-14

申请号：DE10042222

申请日：2000-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: The CFRAM arrangement has a number of memory cells each consisting of a ferroelectric storage capacitor and a selection transistor. Each block of selection transistors is associated with a block-select-transistor. The selection transistors and the block-select-transistor are arranged between a plate line and a bit line and the selection transistors are each connected to word lines. The selection transistors are depletion type FETs. The CFRAM arrangement has a number of memory cells (Z0-Z3) each consisting of a ferroelectric storage capacitor (Cferro0...) and a selection transistor (Tdep10..). Each block of selection transistors is associated with a block-select-transistor (TEnh). The selection transistors and the block-select-transistor are arranged between a plate line (PL) and a bit line (BL) and the selection transistors are each connected to word lines (WL0...). The selection transistors are depletion type field effect transistors.

公开(公告)号：DE10034083C1

公开(公告)日：2002-03-14

申请号：DE10034083

申请日：2000-07-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10 ,  H01L23/528

Abstract: A memory matrix based on at least one cell array of column lines and row lines in which at least two column- or row-lines change their location relative to one another i.e. they cross-over one another. The memory matrix has cell arrays stacked in layers one above the other, and in which in each case the column- or row-lines of different layers lie mainly mutually adjacent, opposite one another.

公开(公告)号：DE10026253A1

公开(公告)日：2001-12-06

申请号：DE10026253

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: G11C17/14 ,  G11C17/18 ,  H01L27/105 ,  H01L23/525

Abstract: A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

公开(公告)号：DE69841838D1

公开(公告)日：2010-09-30

申请号：DE69841838

申请日：1998-06-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  DEBROSSE JOHN

IPC: H01L21/8242 ,  H01L27/108 ,  G11C11/4097

公开(公告)号：DE50015406D1

公开(公告)日：2008-11-27

申请号：DE50015406

申请日：2000-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS DR

IPC: G11C11/406 ,  G11C14/00 ,  G11C11/22

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.