公开(公告)号：DE102005008391B3

公开(公告)日：2006-08-03

申请号：DE102005008391

申请日：2005-02-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ROEHR THOMAS

IPC: H01L21/8239 ,  G11C11/22 ,  G11C11/56 ,  H01L27/105

Abstract: The method involves applying a ferroelectric layer with a ferroelectric material on another ferroelectric layer. A structured etching mask is applied on the former layer. Trenches are etched by the former layer under application of the mask. The trenches are filled with a conductive electrode material to form capacitor electrodes so that capacitor electrodes in the trenches with the areas of the layers form a ferroelectric capacitor. An independent claim is also included for ferroelectric RAM-memory cells with ferroelectric capacitor for storing more than two states.

公开(公告)号：DE60305668D1

公开(公告)日：2006-07-06

申请号：DE60305668

申请日：2003-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOACHIM HANS-OLIVER ,  ROEHR THOMAS

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12 ,  G11C11/22

Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, -0.5 to -1.0V. This increases the effective plateline pulse (V PLH ) to V PLH +the magnitude of the negative voltage. This results in an increase in the difference between V HI and V L0 read signals, thereby increasing the sensing window.

公开(公告)号：DE102004061548A1

公开(公告)日：2006-06-29

申请号：DE102004061548

申请日：2004-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS ,  GRUENING-VON-SCHWERIN ULRIKE ,  ROEHR THOMAS

IPC: H01L27/24

Abstract: The memory cell matrix has the solid electrolyte memory cells which covers a layer pile (CC, R, PL), a word line (WL), a bit line (BL) and a plate line (PL) that are controlled by means of a selection transistor (T) and exhibits a common plate electrode (PL) which is connected to a common plate line. An independent claim is also included for: (a) manufacture of memory cell matrix; and (b) apparatus with a memory element.

公开(公告)号：DE102004047666A1

公开(公告)日：2006-04-13

申请号：DE102004047666

申请日：2004-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G11C7/14 ,  G11C11/4197 ,  G11C16/28

Abstract: A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitor has a reference memory cell with a reference resistor which is connected between the ground terminal and a reference capacitor, in which case, during the reading operation of the memory cell, the memory cell and the reference memory cell are switched on in order to charge or discharge the capacitor and the reference capacitor, and an evaluation device evaluates the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell.

公开(公告)号：DE102004041894B3

公开(公告)日：2006-03-09

申请号：DE102004041894

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SYMANCZYK RALF ,  ROEHR THOMAS

IPC: G11C16/02

Abstract: A conductive bridge RAM (CBRAM) comprises memory cells on a base of active solid electrolyte (13) of alterable resistance embedded between two electrodes (BE,TE) applying given electric fields to switch between high resistance OFF and low resistance ON states. Resistive material (10) is embedded between the electrodes parallel to the electrolyte. An independent claim is also included for a production process for the above.

公开(公告)号：DE10393791T5

公开(公告)日：2005-10-06

申请号：DE10393791

申请日：2003-11-13

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： ROEHR THOMAS ,  JACOB MICHAEL ,  REHM NORBERT ,  TAKASHIMA DAISABURO

IPC: G11C11/22

Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

公开(公告)号：DE10102432B4

公开(公告)日：2005-09-22

申请号：DE10102432

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JACOB MICHAEL ,  ROEHR THOMAS

IPC: G11C29/12 ,  G11C29/40 ,  G11C11/22 ,  G11C29/00

公开(公告)号：DE10132849A1

公开(公告)日：2003-01-23

申请号：DE10132849

申请日：2001-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C8/12 ,  G11C11/16 ,  G11C11/15

Abstract: The memory elements are provided in memory areas (2) to which selection devices (5,7) are assigned. The memory areas are selectively controlled using each selection device during operating mode.

公开(公告)号：DE10002374C2

公开(公告)日：2002-10-17

申请号：DE10002374

申请日：2000-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE10061693A1

公开(公告)日：2002-06-27

申请号：DE10061693

申请日：2000-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: The operating method has the plate lines (PL) associated with a group (20) of memory cells (10) combined, with the potentials of the combined plate lines for all the memory cells in the group altered simultaneously or in common at a relatively rapid variation rate, obtained by providing a relatively small plate line impedance.