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    51.
    发明专利
    未知

    公开(公告)号：DE102004060171B4

    公开(公告)日：2006-09-28

    申请号：DE102004060171

    申请日：2004-12-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  SPECHT MICHAEL

    IPC: H01L27/115 ,  H01L21/8247

    Abstract: The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

    53.
    发明专利
    未知

    公开(公告)号：DE102004033148A1

    公开(公告)日：2006-02-09

    申请号：DE102004033148

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer. A substrate is secured over the patterned electrically conductive layer, and material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered. Furthermore, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.

    54.
    发明专利
    未知

    公开(公告)号：DE102004033147A1

    公开(公告)日：2006-02-09

    申请号：DE102004033147

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A method for fabricating a double-gate transistor including defining an active area on an SOI substrate, forming a first gate region on the SOI substrate, forming source/drain regions made of silicon-germanium in the active area, forming a channel region from the silicon layer of the SOI substrate, forming a layer having a planar surface above the SOI substrate, the source/drain regions, and the first gate region, bonding a second wafer to the planar surface, and forming a second gate region opposite the first gate region.

    55.
    发明专利
    未知

    公开(公告)号：DE102004032917A1

    公开(公告)日：2006-01-26

    申请号：DE102004032917

    申请日：2004-07-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  HOFMANN FRANZ

    IPC: H01L21/336 ,  H01L29/78

    Abstract: In a process for producing a layer arrangement, a first layer is formed with a thickness on a first side of a substrate, which thickness is greater than a minimum thickness for epitaxial growth, a second layer is epitaxially grown on the first layer, and a third layer is formed on the second layer. Furthermore, a handling wafer is bonded to the third layer, the substrate is removed from a second side, which is the opposite side to the first side of the substrate, and the first layer is thinned in subregions from the second side, so that after the thinning the thickness of the first layer is lower than a minimum thickness for epitaxial growth.

    59.
    发明专利
    未知

    公开(公告)号：DE10158018A1

    公开(公告)日：2003-06-12

    申请号：DE10158018

    申请日：2001-11-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SPECHT MICHAEL ,  STAEDELE MARTIN ,  ROESNER WOLFGANG

    IPC: H01L29/15 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115

    Abstract: The invention relates to a layer assembly and to a method for operating a layer assembly as a data memory. The layer assembly comprises a layer structure, which is located between a first and a second electrode region and provided with an electrically non-conductive layer located on the first electrode region, with a number of potential well layers each having at least one energy level and being covered on both sides by a tunnel layer, and with a charge storage layer that is located between the electrically non-conductive tunnel layer and the potential well layers. The potential well layers are disposed so that, in the absence of an electrical voltage between the first electrode region and the second electrode region, their energy levels are offset with regard to one another whereby rendering the potential well layers electrically non-conductive and, in the event of an applied predetermined electrical voltage between the first electrode region and the second electrode region, the energy levels of the potential well layers are offset with regard to one another whereby rendering the potential well layers electrically conductive.

    60.
    发明专利
    未知

    公开(公告)号：DE10137217A1

    公开(公告)日：2003-02-27

    申请号：DE10137217

    申请日：2001-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  SCHULZ THOMAS

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

    Abstract: A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.

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