公开(公告)号：DE602008002277D1

公开(公告)日：2010-10-07

申请号：DE602008002277

申请日：2008-04-21

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： LA ROSA FRANCESCO ,  CONTE ANTONINO

IPC: G11C16/22

公开(公告)号：DE602005010403D1

公开(公告)日：2008-11-27

申请号：DE602005010403

申请日：2005-05-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  SBERNO GIAMPIERO ,  MICCICHE MARIO ,  CASTALDO ENRICO

IPC: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

公开(公告)号：DE60118697D1

公开(公告)日：2006-05-24

申请号：DE60118697

申请日：2001-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G05F3/30

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier (31). The bandgap stage is formed by a first and a second bandgap branch (2, 3) parallel-connected; the first bandgap branch (2) comprises a first diode (6) and a transistor (5), series-connected and forming a first output node (10); the second bandgap branch (3) comprises a second diode (9) and a second transistor (7) series-connected and forming a second output node (11). The operational amplifier (31) has inputs (31a, 31b) connected to the output nodes (10, 11) of the bandgap stage (18). An amplifier current detecting stage (40) is connected to the outputs (37a, 38a) of the operational amplifier (31) and supplies a current (IRES) related to the current drawn by the operational amplifier (31). A diode current detecting stage (41) is connected to the output (40c) of the amplifier current detecting stage (40) and to an output (38a) of the operational amplifier (31) and supplies a current (ID) related to the current (I) flowing in the first diode (6). An output stage (33) transforms this current into a stabilized voltage.

公开(公告)号：IT1319597B1

公开(公告)日：2003-10-20

申请号：ITMI20002763

申请日：2000-12-20

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  LA ROCCA ROSANNA MARIA ,  MATRANGA GIOVANNI

IPC: G11C16/28

Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

公开(公告)号：IT1314042B1

公开(公告)日：2002-12-03

申请号：ITMI992119

申请日：1999-10-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO

IPC: G11C7/06

Abstract: A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current. The differential comparator circuit compares the first and second voltages for providing a logic value relegates to a state of the memory cell to be read.

公开(公告)号：ITMI992149A1

公开(公告)日：2001-04-16

申请号：ITMI992149

申请日：1999-10-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO ,  ZERILLI TOSSAMO

IPC: G11C7/06 ,  G11C7/14

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

公开(公告)号：ITMI992119A1

公开(公告)日：2001-04-11

申请号：ITMI992119

申请日：1999-10-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO

IPC: G11C7/06

Abstract: A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current. The differential comparator circuit compares the first and second voltages for providing a logic value relegates to a state of the memory cell to be read.

公开(公告)号：ITMI992119D0

公开(公告)日：1999-10-11

申请号：ITMI992119

申请日：1999-10-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO

IPC: G11C7/06

Abstract: A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current. The differential comparator circuit compares the first and second voltages for providing a logic value relegates to a state of the memory cell to be read.