公开(公告)号：DE69821560D1

公开(公告)日：2004-03-18

申请号：DE69821560

申请日：1998-07-28

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

公开(公告)号：FR2839388A1

公开(公告)日：2003-11-07

申请号：FR0205539

申请日：2002-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  DUTARTRE DIDIER ,  BOEUF FREDERIC

IPC: H01S5/34 ,  H01L33/00 ,  H01L21/336 ,  H04L9/00

Abstract: An integrated circuit, incorporating a semiconductor device forming the source of a single photon, comprises on a silicon substrate (SB): (a) a MOS transistor (TR) having a grid in the shape of a mushroom, capable of delivering on its drain, in a controlled manner, a single electron in response to a control voltage applied on its grid; (b) at least one compatible silicon quantum box (BQ), electrically coupled to the drain region (D) of the transistor, and capable of emitting a single photon on the reception of a single electron emitted by the transistor. Independent claims are also included for: (a) a cryptographic device incorporating this integrated circuit; (b) a method for the fabrication of this integrated circuit; (c) a method for the emission of a single photon using this integrated circuit.

公开(公告)号：FR2806831B1

公开(公告)日：2003-09-19

申请号：FR0003845

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  DUTARTRE DIDIER ,  BAUDRY HELENE

IPC: H01L21/331 ,  H01L29/737

Abstract: A method for the fabrication of a bipolar transistor consists of forming, using non-selective epitaxy, a semiconductor region with a silicon-germanium heterojunction (1) extending over an active region (ZA) of a semiconductor substrate and an insulating region (STI) delimiting the active region, and incorporating the region of the intrinsic base of the transistor; an emitter region (8) situated above the active region and coming into contact with the upper surface of the heterojunction semiconductor region (1); a layer of polysilicon (30) forming the region of the extrinsic base of the transistor, situated either side of the emitter region (8) and separated from the heterojunction semiconductor region by a separation layer incorporating an electrical liaison conductor (74) part situated in the external neighbourhood of the emitter region, this liaison part assuring an electrical contact between the extrinsic base and the intrinsic base. An Independent claim is included for such a bipolar transistor.

公开(公告)号：FR2784501B1

公开(公告)日：2003-01-31

申请号：FR9812755

申请日：1998-10-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065

Abstract: Forming a deposit of silicon by vapor phase epitaxy on silicon substrate having zones containing high concentration dopants including boron, and avoiding self-doping of the epitaxial layer with boron, comprises introducing chlorinated gas to etch the substrate within a thickness below 100 nm, before forming the epitaxial layer while the substrate is held at high temperature.

公开(公告)号：FR2813707A1

公开(公告)日：2002-03-08

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: Fabrication of a bipolar transistor on a monocrystalline silicon substrate (1) with a first type of conductivity incorporates a stage of carbon implantation at the surface of the substrate followed by annealing, before epitaxial formation of the base of the transistor in the form of a multi-layer (T) semiconductor incorporating at least one lower layer (4), a median heavily doped layer (5) with a second type of conductivity and a upper layer (6) which contacts a heavily doped emitter (9) with the first type of conductivity. An Independent claim is included for a hetero-junction bipolar transistor produced.

公开(公告)号：FR2803091B1

公开(公告)日：2002-03-08

申请号：FR9916283

申请日：1999-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  FELLOUS CYRIL

IPC: H01L21/223 ,  H01L21/331 ,  H01L21/8222

公开(公告)号：FR2798195A1

公开(公告)日：2001-03-09

申请号：FR9911142

申请日：1999-09-02

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  OBERLIN JEAN CLAUDE

IPC: G01N23/20 ,  H01L21/20

Abstract: The x-ray diffraction spectrum of the structure is measured. The diffraction spectra of a monocrystalline silicon substrate, and a monocrystalline silicon substrate completely covered with a layer of monocrystalline SiGe, are simulated. Simulated spectra are added, assigning weights (a) and (1-a), to obtain a summed spectrum. The summed spectrum is compared with the measured spectrum. Simulation parameters and weighting (a) are adjusted, to reduce the difference between summed, and measured spectra.

公开(公告)号：FR2783093B1

公开(公告)日：2000-11-24

申请号：FR9811221

申请日：1998-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

IPC: H01L21/02 ,  H01L29/92

Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

公开(公告)号：FR3046492A1

公开(公告)日：2017-07-07

申请号：FR1563507

申请日：2015-12-31

Applicant: ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： BERTHELON REMY ,  DUTARTRE DIDIER ,  MORIN PIERRE ,  ANDRIEU FRANCOIS ,  BAYLAC ELISE

IPC: H01L21/331 ,  H01L21/76

Abstract: L'invention concerne un procédé de réalisation d'un transistor comprenant les étapes suivantes : a) former une couche semiconductrice (52) s'étendant sur une couche isolante ; b) oxyder thermiquement la couche semiconductrice sur toute son épaisseur selon deux barres (38) s'étendant dans la direction de la largeur de grille du transistor; et c) former des tranchées d'isolement orientées dans la direction de la longueur de grille du transistor, la couche semiconductrice étant contrainte avant ou après l'étape a).

公开(公告)号：FR3019373A1

公开(公告)日：2015-10-02

申请号：FR1452845

申请日：2014-03-31

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JAOUEN HERVE

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/763 ,  H01L29/04

Abstract: Procédé de réalisation d'une plaque de semi-conducteur adaptée pour la fabrication d'un substrat SOI, comprenant les étapes suivantes : - réalisation, sur la face supérieure (2) d'un support semi-conducteur (1), d'une première couche (4) de semi-conducteur polycristallin; puis formation d'une zone d'interface (12) sur la face supérieure (7) de ladite première couche (4), ladite zone d'interface (12) présentant une structure distincte de la structure cristalline celle de ladite première couche (4) ; puis réalisation sur ladite zone d'interface (12), d'une deuxième couche (14) de semi-conducteur polycristallin.