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106 records (took 0.026 seconds)

    56.
    发明专利
    未知

    公开(公告)号：DE60129928D1

    公开(公告)日：2007-09-27

    申请号：DE60129928

    申请日：2001-04-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C11/56 ,  G11C7/06 ,  G11C7/22 ,  G11C16/28 ,  G11C16/32

    Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (10) with a constant current (I) by means of a first capacitive element (23), integrating said current (I) in a time interval ( DELTA t), and controlling the duration of the time interval ( DELTA t) in such a way as to compensate for any deviations in the current (I) from a nominal value. In particular, a reference current (IR) is supplied to a reference cell (101) by means of a second capacitive element (122); next, a first voltage (Var) present on the second capacitive element (122) is measured; finally, the memory cell (10) is deactivated when the first voltage (Var) is equal to a second voltage (Vref), which is constant.

    59.
    发明专利
    未知

    公开(公告)号：DE69921974D1

    公开(公告)日：2004-12-23

    申请号：DE69921974

    申请日：1999-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  ZAMMATTIO MATTEO ,  CAMPARDO GIOVANNI

    IPC: G11C16/06 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/08

    Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, VNEG) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

    60.
    发明专利
    未知

    公开(公告)号：DE69916783D1

    公开(公告)日：2004-06-03

    申请号：DE69916783

    申请日：1999-02-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C16/02 ,  G11C11/56

    Abstract: The sensing circuits (30, 31, 32) comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit (32) associated with the lowest reference current (IR3) amplifies (33b) the cell current more than the other sensing circuits (30, 31) and to the respective reference current (33c). The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current (IR3) may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution (IM3), retaining the possibility of discriminating between the different logic levels.

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