公开(公告)号：EP1498905A2

公开(公告)日：2005-01-19

申请号：EP04023387.6

申请日：1998-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: G11C16/20 ,  G11C16/30 ,  G11C5/14 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/20 ,  G11C2207/2227

Abstract: An operating voltage selection circuit for non-volatile semiconductor memories, whose particularity resides in the fact that it comprises:

-- means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell;
-- memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage;
-- output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and
-- means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.

Abstract translation: 装置（1），用于读取至少一个一次性可编程非易失性存储单元（10），适于产生一个 - ：操作电压选择电路，用于非易失性半导体存储器，谁的特殊性驻留在factthat它包括 信号（LV），其指示非易失性存储器的操作电压，这取决于存储器单元的编程的或非编程的状态的请求的类型; - 存储器使能装置（5），其包含逆变器（30，31）的与设置有装置（32），用于修改所述逆变器的开关阈值作为信号的函数的确指示工作电压的请求的类型; - 输出装置（2），其连接到用于存储的和所述存储器的输出端的感测数据，用于修改所述逆变器的输出电流为包括CMOS反相器（20，50）和装置（23） 信号（LV），用于指示工作电压的所请求的类型的函数; 对于存储器，其包括晶体管的多个的内部同步（40，41，42），其连接在串联/并联配置装置（8），所有这些是确定性由信号（LV），用于指示操作的请求的类型开采 - 和 电压，以便产生用于所述存储器的内部同步信号（CK1，CK2，CK3）。

公开(公告)号：EP0805479B1

公开(公告)日：2004-03-17

申请号：EP96830244.8

申请日：1996-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: H01L21/00 ,  H01L27/105 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11543

公开(公告)号：EP1365417A1

公开(公告)日：2003-11-26

申请号：EP02425293.4

申请日：2002-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：EP0797209B1

公开(公告)日：2002-12-11

申请号：EP96830129.1

申请日：1996-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C7/00

CPC classification number: G11C7/1006

公开(公告)号：EP1174881A1

公开(公告)日：2002-01-23

申请号：EP00830438.8

申请日：2000-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: G11C7/16 ,  G11C16/18

CPC classification number: G11C16/102 ,  G11C7/16 ,  G11C16/18

Abstract: Integrated circuit (106;106') capable of storing data in digital format, particularly for application in a memory card which can be associated for operation with an external acquisition system and an external processing system, comprising: input/output means (2',114',7',122) for receiving the data from the external acquisition system or from the external processing system, for sending the data to the external processing apparatus and for receiving a digital circuit-command signal from the said system and from the said apparatus; a non-volatile electrically programmable memory (101) for storing the said digital data, comprising a first terminal (133) for an electrical programming signal capable of enabling the storage of the data available on the said input/output means and a second terminal (131) for an electrical reading signal capable of enabling the output of the data from the memory to make them available on the input/output means; memory control means (111) connected to the said first and second terminals and to the said input/output means to generate the electrical memory-programming and memory-reading signals from the said command signal. The memory is of the type which can be erased by exposure to electromagnetic radiation, particularly ultraviolet radiation, to permit the non-electrical erasure of the stored data. The integrated circuit can be incorporated in a memory card whose outer casing is provided, at the position of the memory, with means (103) which are transparent to electromagnetic radiation.

Abstract translation: 能够以数字格式存储数据的集成电路（106; 106'），特别是用于可与外部采集系统和外部处理系统相关联的存储卡中的应用，包括：输入/输出装置（2'， 114'，7'，122），用于从外部采集系统或外部处理系统接收数据，用于将数据发送到外部处理装置并从所述系统接收来自所述系统的数字电路命令信号 仪器; 用于存储所述数字数据的非易失性电可编程存储器（101），包括用于能够存储在所述输入/输出装置上可用的数据的电气编程信号的第一终端（133）和第二终端 131），用于能够使来自存储器的数据的输出使其在输入/输出装置上可用的电气读取信号; 连接到所述第一和第二端子和所述输入/输出装置的存储器控​​制装置（111），以从所述命令信号产生电存储器编程和存储器读取信号。 存储器是通过暴露于电磁辐射特别是紫外线辐射而被擦除的类型，以允许对存储的数据进行非电擦除。 集成电路可以在存储器的位置处装配有外壳的存储卡中，具有对电磁辐射透明的装置（103）。

公开(公告)号：EP1160794A1

公开(公告)日：2001-12-05

申请号：EP00830392.7

申请日：2000-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C11/56 ,  G11C16/28

CPC classification number: G11C7/1072 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: The invention relates to a circuit structure (1) for programming data in reference cells (3) of an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix of multi-level memory cells and at least one corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell (3) is incorporated, along with other cells of the same type, to a reference cell sub-matrix (4) which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode.
The bit lines of the sub-matrix (4) branch off to a series of switches (9) which are individually operated by respective control signals REF(i) issued from a logic circuit (8) with the purpose of selectively connecting the bit lines to a single external I/O terminal (10) through a single addressing line (11) of the access DMA mode.

Abstract translation: 本发明涉及一种用于对电可编程/可擦除集成非易失性存储器件的参考单元（3）中的数据进行编程的电路结构（1），包括多级存储器单元的矩阵和至少一个对应的参考单元 在读取阶段期间与相应的存储器单元进行比较。 参考单元（3）与相同类型的其他单元一起并入参考单元子矩阵（4），该参考单元子矩阵在结构上独立于存储单元矩阵并且在DMA模式下从外部直接访问。 子矩阵（4）的位线分支到由逻辑电路（8）发出的相应控制信号REF（i）分别操作的一系列开关（9），目的是选择性地连接位线 通过访问DMA模式的单个寻址线（11）连接到单个外部I / O端子（10）。

公开(公告)号：EP1143454A1

公开(公告)日：2001-10-10

申请号：EP00830239.0

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: The integrated device (100) comprises a PMOS transistor (101) and a voltage selector (1) having an output (6g) connected to the bulk terminal (101d) of the PMOS transistor (101). The voltage selector (1) comprises an input stage (2) supplying (2c) a supply voltage (Vdd) or a programming voltage (Vpp) according to whether the device (100) is in a reading step or in a programming step; a comparator (3) connected to the output (2c) of the input stage (2), receiving a boosted voltage (Vboost), and generating (3g) a first control signal (OC), the state whereof depends upon the comparison of the voltages at the inputs of the comparator (3); a logic circuit (4) connected to the output (3g) of the comparator (3) and generating a second control signal (VDDIS), the state whereof depends upon the state of the first control signal (OC) and of a third-level signal (VTL); and a switching circuit (6) controlled by the first control signal (OC), by the second control signal (VDDIS), and by the third-level signal (VTL) and supplying (6g) each time the highest among the supply voltage (Vdd), the boosted voltage (Vboost), and the programming voltage (Vpp).

Abstract translation: 集成器件（100）包括PMOS晶体管（101）和电压选择器（1），其具有连接到PMOS晶体管（101）的体积端子（101d）的输出（6g）。 电压选择器（1）包括根据装置（100）是处于读取步骤还是编程步骤中的（2c）供应电压（Vdd）或编程电压（Vpp）的输入级（2） 连接到输入级（2）的输出（2c）的比较器（3），接收升压电压（Vboost），并产生（3g）第一控制信号（OC），其状态取决于 比较器（3）输入端的电压; 连接到比较器（3）的输出（3g）并产生第二控制信号（VDDIS）的逻辑电路（4），其状态取决于第一控制信号（OC）的状态和第三级 信号（VTL）; 以及由第一控制信号（OC），第二控制信号（VDDIS）和第三电平信号（VTL）控制的开关电路（6），并且每次在电源电压（ Vdd），升压电压（Vboost）和编程电压（Vpp）。

公开(公告)号：EP1143451A1

公开(公告)日：2001-10-10

申请号：EP00830238.2

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: The charge pump (1) comprises a phase-generator circuit (6) generating phase signals (A, B) and comprising an oscillator circuit (12.1-12.3) supplying a clock signal (CK), a current-limitation circuit (24.1-24.3) to limit the current flowing in the oscillator circuit, and a control circuit (26') supplying on an output (32a) a control signal (V REF ) supplied to the current-limitation circuit. The control circuit (26') comprises a first current mirror (60) connected to a ground line (22), a second current mirror (62) connected to a supply line (20), a cascode structure (64), arranged between the first and the second current mirrors (60, 62) and connected to the output (32a) of the control circuit (26') to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line, and a compensation circuit (70) to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line and by slow variations in temperature.

Abstract translation: 电荷泵（1）包括产生相位信号（A，B）的相位发生器电路（6），并且包括提供时钟信号（CK）的振荡器电路（12.1-12.3），电流限制电路（24.1-24.3 ）以限制在振荡器电路中流动的电流，以及向输出（32a）提供提供给电流限制电路的控制信号（VREF）的控制电路（26'）。 控制电路（26'）包括连接到地线（22）的第一电流镜（60），连接到电源线（20）的第二电流镜（62），共源共栅结构（64） 第一和第二电流镜（60,62），并且连接到控制电路（26'）的输出端（32a），以补偿由控制信号（VREF）的电位（VDD）之间的尖锐相对变化引起的对控制信号 地线的电源线和电位（VGND）以及补偿电路（70），用于补偿由供电线的电位（VDD）与电位之间的尖锐相对变化引起的对控制信号（VREF）的影响 （VGND）和温度变化缓慢。

公开(公告)号：EP0978844A1

公开(公告)日：2000-02-09

申请号：EP98830491.1

申请日：1998-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Calligaro, Cristiano ,  Rolandi, Paolo ,  Gastaldi, Roberto ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5634

Abstract: A multilevel memory device comprises an array of multilevel memory cells (M 1j - M kj , M 1z - M kz ) arranged in rows (WL 1 - WL k ) and columns (BL j , BL z ), each memory cell being capable of being programmed in m = 2 n ( n > 1) distinct programming states, and a sensing arrangement for sensing the memory cells, the sensing arrangement comprising at least ( m - 1) reference columns (BL ref,i , BL ref,h ) of memory cells. The reference columns comprises a number of memory cells substantially identical to the number of memory cells of each column of the array, a smaller number of memory cells (M ref,i , M, ref,h ) of each reference column being multilevel reference memory cells programmed in a respective reference programming state and activatable for sinking a respective reference current (I R,0 ,I R,1 ,I R,2 ), the remaining larger number of memory cells of each reference column being dummy non-conductive memory cells (M dumr,1i - M dumr,ki , M dumr,1h - M dumr,kh ) structurally identical to the reference memory cells and to the memory cells of the array.

Abstract translation: 多级存储器件包括以行（WL1-WLK）和列（BLj，BLz）排列的多级存储器单元阵列（M1j-Mkj，M1z-Mkz），每个存储器单元能够被编程为m = 2 1）不同的编程状态，以及用于感测存储器单元的感测装置，所述感测装置包括至少（m-1）个存储器单元的参考列（BLref，i，BLref，h）。 参考列包括与阵列的每列的存储单元的数量基本相同的多个存储器单元，每个参考列的较小数量的存储器单元（Mref，i，M，ref，h）是多电平参考存储器单元 编程在相应的参考编程状态并且可激活以吸收相应的参考电流（IR，0，IR，1，IR，2），每个参考列的剩余较大数量的存储单元是虚拟非导电存储器单元（Mdumr， 1i-Mdumr，ki，Mdumr，1h-Mdumr，kh）在结构上与参考存储器单元和阵列的存储器单元相同。

公开(公告)号：EP0939408A1

公开(公告)日：1999-09-01

申请号：EP98830104.0

申请日：1998-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: G11C16/00 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/20 ,  G11C2207/2227

Abstract: An operating voltage selection circuit for non-volatile semiconductor memories, whose particularity resides in the fact that it comprises:

-- means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell;
-- memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage;
-- output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and
-- means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.

Abstract translation: 一种用于非易失性半导体存储器的工作电压选择电路，其特殊性在于其包括：用于读取至少一个一次性可编程非易失性存储器单元（10）的装置（1），适用于产生信号（ LV），其指示依赖于存储器单元的编程或非编程状态的非易失性存储器的所请求类型的工作电压; 存储器使能装置（5），其包括逆变器（30,31），并且设置有用于根据指示所请求的工作电压类型的信号来修改逆变器的开关阈值的装置（32） 输出装置（2），其连接到用于感测存储器的数据和存储器的输出端的装置，包括CMOS反相器（20,50）和用于修改逆变器的输出电流作为功能的装置（23） 用于指示所请求的工作电压类型的信号（LV）; 以及用于存储器的内部同步的装置（8），其包括由串联/并联配置连接的多个晶体管（40,41,42），所述晶体管由用于指示所请求类型的工作电压的信号（LV）确定， 以产生用于存储器的内部同步的信号（CK1，CK2，CK3）。