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公开(公告)号:US11895776B2
公开(公告)日:2024-02-06
申请号:US17278782
申请日:2019-09-20
Applicant: Proterial, Ltd.
Inventor: Takahiro Umeyama
CPC classification number: H05K1/189 , G01L9/0041 , G01L9/04 , G01L19/141 , G05D7/06 , H05K1/115 , H05K1/181 , H05K3/323 , H05K2201/09372 , H05K2201/09836 , H05K2201/10151
Abstract: In a flexible printed wiring board (1), a first electrical conduction pattern (4) prepared on the first surface (3a) on which a bare chip (2) is mounted is prepared only inside a mounting region (3c) of the bare chip. Preferably, the first electrical conduction patterns (4) are prepared so as to avoid positions opposite to test electrodes (2b) which the bare chip comprises. Thereby, in the flexible printed wiring board used for mounting the bare chip, occurrence of malfunction resulting from electrical connection with a part other than a bump of the bare chip can be certainly prevented, and reliability of various devices using the bare chip can be improved.
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公开(公告)号:US20230300987A1
公开(公告)日:2023-09-21
申请号:US18175898
申请日:2023-02-28
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Masahiro KYOZUKA
CPC classification number: H05K3/0011 , H05K1/05 , H05K2201/10204 , H05K2201/093 , H05K2201/09372
Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.
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公开(公告)号:US20190207327A1
公开(公告)日:2019-07-04
申请号:US16233310
申请日:2018-12-27
Inventor: Liang Huang , Bruce Allen Champion
CPC classification number: H01R4/02 , H01R12/52 , H01R12/7082 , H01R13/50 , H01R13/502 , H05K1/11 , H05K3/34 , H05K2201/09372
Abstract: A circuit board comprises a row of solder pads adapted to be soldered to a row of contacts of a connector, a plurality of first conductive vias, and a plurality of second conductive vias. The contacts include a plurality of ground contacts and a plurality of signal contacts. The solder pads include a plurality of ground solder pads each soldered to a solder foot of one of the ground contacts and a plurality of signal solder pads each soldered to a solder foot of one of the signal contacts. The first conductive vias correspond to and are electrically connected to the ground solder pads and are electrically connected to each other by a first connection bar. The second conductive vias correspond to and are electrically connected to the ground solder pads and are electrically connected to each other by a second connection bar. The solder foot of each of the ground contacts is disposed between one of the first conductive vias and one of the second conductive vias.
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公开(公告)号:US20180242462A1
公开(公告)日:2018-08-23
申请号:US15897560
申请日:2018-02-15
Applicant: CANON KABUSHIKI KAISHA
Inventor: Kunihiko Minegishi , Mitsutoshi Hasegawa , Takashi Sakaki
CPC classification number: H05K3/3421 , H05K1/111 , H05K1/181 , H05K3/3436 , H05K2201/09372 , H05K2201/0989 , H05K2201/10674 , H05K2201/10719 , H05K2201/10734 , H05K2201/10977 , H05K2203/1305
Abstract: An electronic component is mounted on the mounting face of a printed wiring board and a plurality of terminals arranged on the mounting face of the printed wiring board are respectively bonded to a plurality of terminals arranged on the bottom surface of the electronic component by means of solder. Solder paste containing powdery solder and thermosetting resin is provided to the plurality of terminals on the mounting face, then the electronic component is mounted on the mounting face of the printed wiring board, and subsequently the solder paste is heated to bond the corresponding terminals by means of molten solder. Thereafter, the molten solder is allowed to solidify and the thermosetting resin separated from the solder paste is allowed to cure in a state where it is held in contact with metal members arranged separately relative to the terminals.
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公开(公告)号:US20180139852A1
公开(公告)日:2018-05-17
申请号:US15351066
申请日:2016-11-14
Applicant: International Business Machines Corporation
Inventor: Bruce J. CHAMBERLIN , Scott B. KING , Joseph KUCZYNSKI , David J. RUSSELL
CPC classification number: H05K3/4076 , H05K1/09 , H05K1/116 , H05K3/002 , H05K3/0038 , H05K3/0047 , H05K3/22 , H05K3/422 , H05K3/429 , H05K3/4644 , H05K2201/0166 , H05K2201/0209 , H05K2201/0347 , H05K2201/09372 , H05K2201/095 , H05K2201/09581 , H05K2203/0723 , H05K2203/0793 , H05K2203/10 , H05K2203/11 , H05K2203/1184
Abstract: In some embodiments, methods include drilling one or a plurality of PTHs with any industrial grade drill to fabricate holes with positive etch back, flooding the PTHs with a dilute solution of an acrylate monomer/oligomer containing an appropriate level of peroxide initiator, polymerizing the acrylate, and then rising the PTHs with the solvent used in the formulation of the acrylate material. In one embodiment, the printed circuit board may include a substrate comprising a plurality of metal layers separated by a plurality of insulating layers; a plurality of plated through holes formed in the substrate, each plated through hole comprising: recesses formed at each insulating layer, copper lands between the recesses, a polymer coating in each recess, and a metal layer lining the plated through hole.
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公开(公告)号:JP6078700B1
公开(公告)日:2017-02-08
申请号:JP2016546529
申请日:2014-10-14
Applicant: アウト カーベル マネージメントゲゼルシャフト ミット ベシュレンクテル ハフツング
Inventor: ワシム ターツェリーネ , ジーモン ベッチャー , フランク グロンヴァルト
CPC classification number: H05K1/145 , H05K1/0209 , H05K1/056 , H05K1/111 , H05K1/142 , H05K1/181 , H05K3/368 , C23C14/042 , H01L23/142 , H01L23/367 , H01L23/3677 , H01L2924/0002 , H05K1/0206 , H05K1/117 , H05K1/182 , H05K2201/09372 , H05K2201/09554 , H05K2201/10166 , H05K2201/10689 , H05K2203/1377 , H05K3/28 , H05K3/282
Abstract: 第1のプリント回路基板及び第2のプリント回路基板を有する回路である。その回路において、エアギャップによって互いに離されているプリント回路基板は、少なくとも1つのパワー半導体によって相互に機械的に接続されている。 【選択図】図7
Abstract translation: 具有第一印刷电路板和所述第二印刷电路板的电路。 在该电路中,其由彼此由空气间隙分隔开的印刷电路板是由至少一个功率半导体机械地连接到彼此。 点域7
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公开(公告)号:JP2017505991A
公开(公告)日:2017-02-23
申请号:JP2016546529
申请日:2014-10-14
Applicant: アウト カーベル マネージメントゲゼルシャフト ミット ベシュレンクテル ハフツング
Inventor: ターツェリーネ ワシム , ベッチャー ジーモン , グロンヴァルト フランク
CPC classification number: H05K1/145 , C23C14/042 , H01L23/142 , H01L23/367 , H01L23/3677 , H01L2924/0002 , H05K1/0206 , H05K1/0209 , H05K1/056 , H05K1/111 , H05K1/117 , H05K1/142 , H05K1/181 , H05K1/182 , H05K3/28 , H05K3/282 , H05K3/368 , H05K2201/09372 , H05K2201/09554 , H05K2201/10166 , H05K2201/10689 , H05K2203/1377 , H01L2924/00
Abstract: 第1のプリント回路基板及び第2のプリント回路基板を有する回路である。その回路において、エアギャップによって互いに離されているプリント回路基板は、少なくとも1つのパワー半導体によって相互に機械的に接続されている。【選択図】図7
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公开(公告)号:US20240196538A1
公开(公告)日:2024-06-13
申请号:US18522664
申请日:2023-11-29
Applicant: TDK Corporation
Inventor: Akihiro MASUDA , Katsuya MIURA , Natsuki KUMAGAI
CPC classification number: H05K1/183 , H05K1/0203 , H05K2201/09372 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003
Abstract: An electronic device comprises chip components aligned along a predetermined first direction and including respective terminal electrodes, and a metal block including an electrode-opposing surface and a mounting surface. The electrode-opposing surface is opposed and connected to the respective terminal electrodes of the chip components continuously along the first direction. The mounting surface is substantially perpendicular to the electrode-opposing surface and is substantially parallel to the first direction to oppose a land pattern when the electronic device is mounted on the land pattern.
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公开(公告)号:US20230380068A1
公开(公告)日:2023-11-23
申请号:US18029945
申请日:2021-09-24
Applicant: Hitachi Astemo, Ltd.
Inventor: Takeshi IGARASHI , Katsuya OYAMA
CPC classification number: H05K1/181 , H01L23/12 , H01L23/3107 , H05K3/3431 , H05K2201/09372
Abstract: An object of the present invention is to provide an electronic control device capable of improving the connection life and reliability of solder connecting a printed circuit board and a QFN type semiconductor package. For this purpose, a printed circuit board 106 includes a first land 109 connected to a first metal terminal 104 via a solder 107, a second land 110 connected to a second metal terminal 105 via a solder 108, a third land 112 disposed on the outer peripheral side of a semiconductor package 101 with respect to the first land 109, and a resist 113 formed on the third land 112 so as to be in contact with the lower surface of a molding resin 103.
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公开(公告)号:US20170165474A1
公开(公告)日:2017-06-15
申请号:US15357500
申请日:2016-11-21
Applicant: The Charles Stark Draper Laboratory, Inc.
Inventor: Maurice S. Karpman , Andrew Meuller
CPC classification number: A61N1/0502 , A61B5/04001 , A61B5/685 , A61B2562/043 , A61B2562/125 , A61N1/0551 , A61N1/36139 , H05K1/028 , H05K1/09 , H05K1/111 , H05K3/0026 , H05K3/40 , H05K3/4644 , H05K3/4682 , H05K2201/05 , H05K2201/09372 , H05K2203/107
Abstract: The present disclosure describes a closely spaced array of penetrating electrodes. In some implementations, the electrodes of the array are spaced less than 50 μm apart. The present disclosure also describes methods for manufacturing the closely spaced array of penetrating electrodes. In some implementations, each row of electrode of the array is manufactured in-plane and then coupled to other rows of electrodes to form an array.
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