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    66.
    发明专利
    未知

    公开(公告)号：DE69833743T2

    公开(公告)日：2006-11-09

    申请号：DE69833743

    申请日：1998-12-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO

    IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78

    Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, comprising a first step of forming a first semiconductor layer (41) of a first conductivity type, a second step of forming a first mask (37) over the top surface of the first semiconductor layer (41), a third step of removing portions of the first mask (37) in order to form at least one opening (51) in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer (41) through the at least one opening (51), a fifth step of completely removing the first mask (37) and of forming a second semiconductor layer (42) of the first conductivity type over the first semiconductor layer (41), a sixth step of diffusing the dopant implanted in the first semiconductor layer (41) in order to form a doped region (220) of the second conductivity type in the first and second semiconductor layers (41, 42). The second step up to the sixth step are repeated at least one time in order to form a final edge structure comprising a number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) of the first conductivity type and at least two columns of doped regions (220, 230, 240, 250, 260) of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) and formed by means of superimposition of the doped regions (220, 230, 240, 250, 260) subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther to the high voltage semiconductor device.

    68.
    发明专利
    未知

    公开(公告)号：DE69631524T2

    公开(公告)日：2004-10-07

    申请号：DE69631524

    申请日：1996-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

    69.
    发明专利
    未知

    公开(公告)号：ITMI20012284A1

    公开(公告)日：2003-04-30

    申请号：ITMI20012284

    申请日：2001-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGRI ANGELO

    IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

    Abstract: The invention relates to an electronic power device (1) of improved structure and fabricated with MOS technology to have at least one gate finger region (3) and corresponding source regions (4) on opposite sides of the gate region (3). This device (1) has at least one first-level metal layer (3',4') arranged to independently contact the gate region (3) and source regions, and has a protective passivation layer (5) arranged to cover the gate region (3). Advantageously, a wettable metal layer (7), deposited onto the passivation layer (5) and the first-level metal layer (4'), overlies said source regions (4). In this way, the additional wettable metal layer (7) is made to act as a second-level metal.

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