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61.发明授权Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors 有权架构是闪速EEPROM，而擦除或一个或多个其它扇区的编程，读取同一时间。
公开(公告)号：EP1327992B1
公开(公告)日：2005-03-30
申请号：EP02425009.4
申请日：2002-01-11
Applicant: STMicroelectronics S.r.l.
Inventor： Silvagni, Andrea , Micheloni, Rino , Campardo, Giovanni
CPC classification number: G11C16/08 , G11C2216/22
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62.发明授权CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching 有权CMOS开关期间在非易失性存储器的低功耗切换用于传输高电压，特别是对行译码器
公开(公告)号：EP1058271B1
公开(公告)日：2004-12-15
申请号：EP99830345.7
申请日：1999-06-04
Applicant: STMicroelectronics S.r.l. , Mitsubishi Electric Corporation
Inventor： Micheloni, Rino , Campardo, Giovanni , Ohba, Atsushi, c/o Mitsubishi Denki K. K. , Carrera, Marcello
IPC: G11C16/12 , H03K19/017
CPC classification number: H03K19/018521 , G11C5/145 , G11C8/10 , G11C11/5621 , G11C16/08 , H03K19/0013 , H03K19/01721
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63.发明公开Non volatile memory device including a predetermined number of sectors 审中-公开NichtflüchtigeSpeichervorrichtung mit einer vorgegebenen Anzahl von Sektoren
公开(公告)号：EP1435625A1
公开(公告)日：2004-07-07
申请号：EP02425808.9
申请日：2002-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Khouri, Osama , Ravasio, Roberto , Micheloni, Rino , Campardo, Giovanni
IPC: G11C29/00
CPC classification number: G11C29/76
Abstract: A non volatile memory of the type comprising a predetermined number of sectors capable of ensuring the operation of the same even with a lower number of defective sectors than a predetermined limit.
Abstract translation: 这种类型的非易失性存储器包括能够确保即使具有比预定极限更少数量的缺陷扇区的扇区的预定数量的扇区。
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64.发明授权Circuit device for providing a hierarchical row decoding in semiconductor memory devices 有权一种用于半导体存储器装置的分层小区解码电路装置
公开(公告)号：EP0991075B1
公开(公告)日：2004-05-06
申请号：EP98830570.2
申请日：1998-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino
IPC: G11C8/00
CPC classification number: G11C16/0416 , G11C8/14
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公开(公告)号：EP1028433B1
公开(公告)日：2004-04-28
申请号：EP99830071.9
申请日：1999-02-10
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C8/14 , G11C11/5621 , G11C16/08
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Patent Agency Ranking66.发明授权Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 失效方法和电路，用于产生一个地址转换信号ATD以调节访问非易失性存储器
公开(公告)号：EP0915477B1
公开(公告)日：2004-03-17
申请号：EP97830576.1
申请日：1997-11-05
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino , Maccarrone, Marco , Zammattio, Matteo
IPC: G11C8/00
CPC classification number: G11C8/18
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67.发明授权Nonvolatile memory with a single-cell reference signal generating circuit for reading memory cells 失效与单细胞参考信号产生电路的非易失性存储器，用于读取的存储器单元
公开(公告)号：EP0814484B1
公开(公告)日：2003-09-17
申请号：EP96830348.7
申请日：1996-06-18
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Micheloni, Rino , Commodaro, Stefano
IPC: G11C16/06
CPC classification number: G11C16/28
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68.发明公开Regulation method for the source voltage in a nonvolatile memory cell during programming and corresponding program circuit 有权一种用于编程非易失性存储器单元期间调节的源极电压和相应的编程电路的方法
公开(公告)号：EP1331644A2
公开(公告)日：2003-07-30
申请号：EP02019433.8
申请日：2002-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Micheloni, Rino , Motta, Maria
IPC: G11C16/30
CPC classification number: G11C16/30
Abstract: The invention relates to a method and a circuit for regulating the source terminal (S) voltage to the of a non-volatile memory cell (3) during the cell programming and/or reading phases. The method comprises a phase of locally regulating said voltage value and consists of comparing the source current (Is) of the cell array (3) with a reference current (Iref). A fraction of the source current (Is) is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels; the comparison result being used for controlling a current generator (25) to inject, into the source terminal (S), the current necessary to keep the predetermined voltage thereof at a constant value.
Abstract translation: 本发明涉及一种方法和用于该单元编程期间调节所述源终端（S）到一个非易失性存储单元（3）的电压和/或读取阶段的电路。 该方法包括在本地调节所述电压值和所述单元阵列（3）的源极电流（IS）与基准电流（IREF）比较的besteht的相位。 源电流（IS）的一小部分被转换为一个电压，并与从作为参考，被编程为具有最高电流电平的分布的存储单元中产生的电压进行比较; 被用于控制的电流发生器（25）注入，到源终端（S）的比较结果，所需的电流为恒定值保持其预定的电压。
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公开(公告)号：EP1052572B1
公开(公告)日：2003-07-30
申请号：EP99830286.3
申请日：1999-05-12
Applicant: STMicroelectronics S.r.l.
Inventor： Campardo, Giovanni , Manstretta, Alessandro , Micheloni, Rino
IPC: G06F11/20
CPC classification number: G11C29/846
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70.发明公开A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法
公开(公告)号：EP1211812A3
公开(公告)日：2003-02-12
申请号：EP00127649.2
申请日：2000-11-23
Applicant: STMicroelectronics S.r.l.
Inventor： Micheloni, Rino , Khouri, Osama , Pierin, Andrea , Gregori, Stefano , Torelli, Guido
CPC classification number: G11C11/56 , G11C27/005 , H03M1/146 , H03M1/361
Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.
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