中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

96 records (took 0.038 seconds)

    Application of a strain-compensated heavily doped etch stop for silicon structure formation
    62.
    发明申请
    Application of a strain-compensated heavily doped etch stop for silicon structure formation 审中-公开
    应变补偿重掺杂蚀刻停止件用于硅结构形成

    公开(公告)号：US20020179563A1

    公开(公告)日：2002-12-05

    申请号：US09873931

    申请日：2001-06-04

    Inventor： Robert D. Horning ,  David W. Burns

    IPC: C23F001/00

    CPC classification number: B81C1/00595 ,  B81B2201/0264 ,  B81C2201/0164

    Abstract: A method of making a silicon micromechanical structure, from a lightly doped silicon substrate having less than

    Abstract translation: 从其中具有小于5×10 19 cm -3的硼的轻掺杂硅衬底制造硅微机械结构的方法。 将硼含量大于7×1019cm-3，锗含量约为1×10 21 cm -3的p +层置于衬底上。 在第二面上形成掩模，然后蚀刻到p +层。 将绝缘体放在p +层上，并在其上制造电子部件。 优选的微机械结构是压力传感器，悬臂加速度计和双网双平面加速度计。 优选的电子部件是介电离子压敏电阻器和共振微束。 该方法可以包括在p +层上形成轻掺杂层以在蚀刻之前形成掩埋的p +层的步骤。

    Silicon membrane with controlled stress
    65.
    发明授权
    Silicon membrane with controlled stress 失效
    具有受控应力的硅膜

    公开(公告)号：US5110373A

    公开(公告)日：1992-05-05

    申请号：US565253

    申请日：1990-08-09

    Applicant: Philip E. Mauger

    Inventor： Philip E. Mauger

    IPC: C23C14/00 ,  C25F3/12 ,  H01L21/3063

    CPC classification number: B81C1/00666 ,  C23C14/0005 ,  C25F3/12 ,  H01L21/3063 ,  B81B2203/0127 ,  B81C2201/0164 ,  Y10S148/159 ,  Y10S438/938 ,  Y10S438/977

    Abstract: A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.

    Abstract translation: 一种制备具有预定应力特性的硅膜的方法。 掺杂硅衬底以产生如期望的膜厚度那样厚的掺杂层。 通过基于其相对于硅的原子直径选择掺杂剂并控制掺杂剂的总浓度和浓度分布来控制掺杂层内的应力。 然后通过电化学蚀刻掉掺杂层下面的衬底形成膜。

    LOW TEMPERATURE PLASMA SI OR SIGE FOR MEMS APPLICATIONS
    66.
    发明申请
    LOW TEMPERATURE PLASMA SI OR SIGE FOR MEMS APPLICATIONS 审中-公开
    用于MEMS应用的低温等离子体SI或SIGE

    公开(公告)号：WO2004013039A3

    公开(公告)日：2004-12-16

    申请号：PCT/US0314930

    申请日：2003-05-13

    Applicant: FREESCALE SEMICONDUCTOR INC

    Inventor： FOERSTNER JUERGEN A ,  SMITH STEVEN M ,  ROOP RAYMOND MERVIN

    IPC: B81B3/00 ,  B81B7/02 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

    CPC classification number: B81C1/0038 ,  B81B2201/018 ,  B81B2201/0292 ,  B81C1/00246 ,  B81C2201/0164 ,  B81C2203/0735 ,  H01G5/18

    Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

    Abstract translation: 提供了一种用于制造MEMS结构（69）的方法。 根据该方法，提供了具有沉积在其上的互连金属（53）的CMOS衬底（51）。 通过等离子体辅助化学气相沉积（PACVD）在基材上形成MEMS结构，该材料选自由硅和硅 - 锗合金组成的组。 伴随使用PACVD的低沉积温度允许这些材料在集成CMOS工艺的后端用于MEMS制造。

    APPLICATIONS OF A STRAIN-COMPENSATED HEAVILY DOPED ETCH STOP FOR SILICON STRUCTURE FORMATION
    67.
    发明申请
    APPLICATIONS OF A STRAIN-COMPENSATED HEAVILY DOPED ETCH STOP FOR SILICON STRUCTURE FORMATION 审中-公开
    用于硅结构形成的应变补偿重金属灭弧室的应用

    公开(公告)号：WO02098788A3

    公开(公告)日：2003-10-09

    申请号：PCT/US0217216

    申请日：2002-06-04

    Applicant: HONEYWELL INT INC

    Inventor： HORNING ROBERT D ,  BURNS DAVID W

    IPC: B81B3/00 ,  B81C1/00 ,  C23F1/00

    CPC classification number: B81C1/00595 ,  B81B2201/0264 ,  B81C2201/0164

    Abstract: A method of making a silicon micromechanical structure, from a lightly doped silicon substrate having less than cm boron therein. A p+ layer having a boron content of greater than 7 x 10 cm and a germanium content of about 1 x 10 cm is placed on the substrate. A mask is formed on the second side, followed by etching to the p+ layer. An insulator is put on the p+ layer and an electronic component is fabricated thereon. Preferred micromechanical structures are pressure sensors, cantilevered accelerometers, and dual web biplane accelerometers. Preferred electronic components are dielectrically isolated piezoresistors and resonant microbeams. The method may include the step of forming a lightly doped layer on the p+ layer to form a buried p+ layer prior to etching.

    Abstract translation: 从其中具有小于5×10 19 cm 3的硼的轻掺杂硅衬底制造硅微机械结构的方法。 具有大于7×10 19 cm -3的硼含量和约1×10 21 cm -3的锗含量的p +层被放置在衬底上。 在第二面上形成掩模，然后蚀刻到p +层。 将绝缘体放在p +层上，并在其上制造电子部件。 优选的微机械结构是压力传感器，悬臂加速度计和双网双平面加速度计。 优选的电子部件是介电离子压敏电阻器和共振微束。 该方法可以包括在p +层上形成轻掺杂层以在蚀刻之前形成掩埋的p +层的步骤。

    METHOD FOR DEPOSITING POLYCRYSTALLINE SIGE SUITABLE FOR MICROMACHINING AND DEVICES OBTAINED THEREOF
    68.
    发明申请
    METHOD FOR DEPOSITING POLYCRYSTALLINE SIGE SUITABLE FOR MICROMACHINING AND DEVICES OBTAINED THEREOF 审中-公开
    用于沉积适用于微机电的多晶硅信号的方法及其获得的器件

    公开(公告)号：WO01074708A2

    公开(公告)日：2001-10-11

    申请号：PCT/IB2001/000765

    申请日：2001-04-05

    IPC: B81C1/00 ,  C23C16/22 ,  H01L21/205 ,  H01L31/0368 ,  H01L31/18 ,  B81C

    CPC classification number: C23C16/22 ,  B81C1/00365 ,  B81C2201/0164 ,  B81C2201/017 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L31/03682 ,  H01L31/1812 ,  Y02E10/546

    Abstract: Method and apparatus of to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers are used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1-x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters are used.

    Abstract translation: 获得沉积的多晶和低应力SiGe层的方法和设备。 这些层用于微机电系统（MEMS）装置或微加工结构。 分析影响多晶层应力的不同参数。 参数包括但不限于：沉积温度; 半导体的浓度（例如，SixGe1-x层中的硅和锗的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。 取决于多晶SiGe生长的特定环境，使用不同的参数值。

    METHOD FOR REDUCING VARIATIONS IN ARRAYS OF MICRO-MACHINED CANTILEVER STRUCTURES USING ION IMPLANTATION
    69.
    发明申请
    METHOD FOR REDUCING VARIATIONS IN ARRAYS OF MICRO-MACHINED CANTILEVER STRUCTURES USING ION IMPLANTATION 审中-公开
    使用离子植入法减少微机械结构的阵列变化的方法

    公开(公告)号：WO01036319A1

    公开(公告)日：2001-05-25

    申请号：PCT/US2000/031358

    申请日：2000-11-15

    IPC: B81B3/00 ,  B81C1/00 ,  G01J5/40

    CPC classification number: B81C1/00666 ,  B81C2201/0164

    Abstract: A method of adjusting the position of a micro-mechanical bi-material cantilever is provided. The bi-material includes a first and a second material and each material has a corresponding thermal expansion coefficient. The method includes implanting ions predominantly into one material of the bi-material to modify internal stress in one of the first and second materials relative to the other material. The deformation of the bi-material is then detected to modulate the implantation of ions thereto.

    Abstract translation: 提供了一种调整微机械双材料悬臂的位置的方法。 双材料包括第一和第二材料，并且每种材料具有相应的热膨胀系数。 该方法包括将离子主要注入双材料的一种材料中以相对于其它材料改变第一和第二材料之一中的内部应力。 然后检测双材料的变形以调制离子的注入。

Patent Agency Ranking