公开(公告)号：US09859036B2

公开(公告)日：2018-01-02

申请号：US14869503

申请日：2015-09-29

Applicant: FUJIFILM Corporation

Inventor： Yasuaki Matsushita ,  Tokihiko Matsumura

IPC: H01B1/22 ,  H05K1/09 ,  C09D5/24 ,  C09D1/00 ,  C09D7/12 ,  H01B3/44 ,  H05K3/12 ,  H05K3/28

CPC classification number: H01B1/22 ,  C08K3/08 ,  C08K5/02 ,  C08K5/13 ,  C08K5/32 ,  C08K5/3475 ,  C08K5/37 ,  C08K5/46 ,  C08K5/49 ,  C08K5/52 ,  C08K2003/0806 ,  C08K2003/0812 ,  C08K2003/0831 ,  C08K2003/085 ,  C09D1/00 ,  C09D5/24 ,  C09D7/40 ,  H01B3/445 ,  H05K1/09 ,  H05K1/092 ,  H05K3/125 ,  H05K3/282 ,  H05K2201/0269 ,  H05K2201/0338 ,  H05K2201/0769

Abstract: A conductive film forming composition includes a fluorine atom-containing migration inhibitor and a metal particle, with the migration inhibitor including at least one selected from the group consisting of compounds represented by General Formulae (1) to (5), (22) and (23) as well as compounds having a group of General Formula (24) and a group of General Formula (25). The conductive film forming composition makes it possible to form a conductive film excellent in conductive characteristics and ion migration inhibiting function.

公开(公告)号：US09807874B2

公开(公告)日：2017-10-31

申请号：US14348428

申请日：2012-09-29

Applicant: KYOCERA Corporation

Inventor： Katsura Hayashi

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/14 ,  H01L23/498 ,  H01L23/13 ,  H01L23/373 ,  H01L23/00 ,  H05K1/18 ,  H05K1/05 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/15321 ,  H05K1/056 ,  H05K1/185 ,  H05K3/4608 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A wiring substrate for improving connection reliability with an electronic component, a component embedded substrate that incorporates an embedded component into the wiring substrate, and a package structure including an electronic component mounted on the wiring substrate or the component embedded substrate. The wiring substrate includes a metal plate, and a wiring layer including a plurality of insulating layers and a conductive layer arranged on the plurality of insulating layers arranged on at least one principal surface of the metal plate. The plurality of insulating layers includes a first insulating layer to contact the principal surface of the metal plate and has a larger thermal expansion rate in the planar direction than the metal plate and a second insulating layer which is laminated on the first insulating layer to contact the first insulating layer and has smaller thermal expansion rate in the planar direction than the metal plate.

公开(公告)号：US09693451B2

公开(公告)日：2017-06-27

申请号：US14380207

申请日：2013-02-20

Applicant: KYOCERA Corporation

Inventor： Tadashi Nagasawa ,  Katsura Hayashi

IPC: H05B3/02 ,  H05K1/03 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K1/036 ,  H05K3/3436 ,  H05K3/4602 ,  H05K3/4661 ,  H05K3/467 ,  H05K3/4673 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: A wiring board (3) according to an embodiment of the present invention includes an inorganic insulating layer (11A); a first resin layer (12A) on one main surface of the inorganic insulating layer (11A); a second resin layer (13A) on another main surface of the inorganic insulating layer (11A); and a conductive layer (8) partially on one main surface of the second resin layer (13A), the one main surface being on an opposite side to the inorganic insulating layer (11A). The inorganic insulating layer (11A) includes a plurality of first inorganic insulating particles (14) which are bound to each other at a part of each of the first inorganic insulating particles and gaps (G) surrounded by the plurality of first inorganic insulating particles (14). A part of the first resin layer (12A) and a part of the second resin layer (13A) are located inside the gaps (G).

公开(公告)号：US20170006701A1

公开(公告)日：2017-01-05

申请号：US15125573

申请日：2014-03-11

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Vincenzo CASASANTA, III

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/12 ,  C08J5/04 ,  B32B5/12 ,  B32B27/08 ,  B32B27/18 ,  B32B27/22 ,  B32B27/36 ,  C08J5/00 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K1/0366 ,  B32B3/266 ,  B32B5/02 ,  B32B5/08 ,  B32B5/12 ,  B32B5/22 ,  B32B5/26 ,  B32B9/02 ,  B32B9/04 ,  B32B25/02 ,  B32B25/042 ,  B32B25/08 ,  B32B27/08 ,  B32B27/18 ,  B32B27/22 ,  B32B27/28 ,  B32B27/281 ,  B32B27/283 ,  B32B27/285 ,  B32B27/286 ,  B32B27/302 ,  B32B27/304 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B27/38 ,  B32B27/40 ,  B32B27/42 ,  B32B2260/021 ,  B32B2260/04 ,  B32B2260/046 ,  B32B2262/04 ,  B32B2262/062 ,  B32B2262/065 ,  B32B2262/10 ,  B32B2262/101 ,  B32B2262/14 ,  B32B2264/0278 ,  B32B2264/105 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/546 ,  B32B2307/7163 ,  B32B2307/75 ,  B32B2457/08 ,  C08J5/005 ,  C08J5/041 ,  C08J2367/04 ,  C08K3/08 ,  C08K2003/0806 ,  H05K1/0353 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/097 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0011 ,  H05K3/1216 ,  H05K3/1241 ,  H05K3/125 ,  H05K3/1275 ,  H05K3/22 ,  H05K3/4038 ,  H05K2201/012 ,  H05K2201/0133 ,  H05K2201/0145 ,  H05K2201/0162 ,  H05K2201/0212 ,  H05K2201/0251 ,  H05K2201/0269 ,  H05K2201/0278 ,  H05K2201/0284 ,  H05K2201/0293 ,  H05K2203/0271 ,  H05K2203/0769 ,  H05K2203/1105 ,  H05K2203/176 ,  H05K2203/178 ,  Y02P70/611 ,  Y02P70/613 ,  C08L67/04

Abstract: Biodegradable printed circuit boards, or PCBs, may be produced from substrate sheets that include at least one biodegradable polymer. In addition, the electrical traces used on the PCBs, may also include a biodegradable polymer incorporated with an electrically conductive material. The PCBs may be composted to degrade the PCBs, and the

Abstract translation: 可生物降解的印刷电路板或PCB可以由包括至少一种可生物降解的聚合物的基材片制成。 另外，PCB上使用的电迹线也可以包括结合有导电材料的可生物降解的聚合物。 PCB可能被堆肥以降解PCBs

公开(公告)号：US20160047766A1

公开(公告)日：2016-02-18

申请号：US14460578

申请日：2014-08-15

Applicant: John Andrew Lebens ,  Ronald Steven Cok ,  Yongcai Wang

Inventor： John Andrew Lebens ,  Ronald Steven Cok ,  Yongcai Wang

IPC: G01N27/12 ,  G01N27/07

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: An imprinted electronic sensor structure on a substrate for sensing an environmental factor includes a cured layer having a layer surface located on the substrate. Spatially separated micro-channels extend from the layer surface into the cured layer. A multi-layer micro-wire is formed in each micro-channel. Each multi-layer micro-wire includes at least a conductive layer and a reactive layer. The reactive layer is exposed to the environmental factor. The conductive layer is a cured electrical conductor located only within the micro-channel and at least a portion of the reactive layer responds to the environmental factor.

Abstract translation: 用于感测环境因素的基板上的印刷电子传感器结构包括具有位于基板上的层表面的固化层。 空间分离的微通道从层表面延伸到固化层。 在每个微通道中形成多层微线。 每个多层微线包括至少一个导电层和一个反应层。 反应层暴露于环境因素。 导电层是仅位于微通道内的固化电导体，并且反应层的至少一部分响应于环境因素。

公开(公告)号：US20150014028A1

公开(公告)日：2015-01-15

申请号：US14094588

申请日：2013-12-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Hwa Young Lee ,  Ho Hyung Ham ,  Jun Ho Bae ,  Ki Seok Kim ,  Eui Jung Jung ,  Ji Hye Shim

IPC: H05K1/02 ,  B32B15/085

CPC classification number: B32B15/085 ,  B32B15/06 ,  B32B15/08 ,  B32B15/092 ,  B32B27/20 ,  B32B27/38 ,  B32B27/42 ,  B32B2264/10 ,  B32B2264/102 ,  B32B2307/206 ,  B32B2307/308 ,  B32B2307/714 ,  B32B2457/08 ,  H05K1/0373 ,  H05K3/387 ,  H05K3/4661 ,  H05K2201/0141 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  Y10T428/265 ,  Y10T428/31511 ,  Y10T428/31692 ,  Y10T428/31938

Abstract: Disclosed herein are an insulating film for a printed circuit board, a resin coated copper (RCC), a flexible copper clad laminate (FCCL), and a printed circuit board manufactured by using the same. More specifically, the RCC, the FCCL, and the printed circuit board manufactured by using the insulating film for the printed circuit board according to the preferred embodiment of the present invention, the insulating film including an insulating layer, and a primer layer formed on one surface of the insulating layer and including a benzocyclobutene (BCB)-based resin, may have a low coefficient of thermal expansion and high peel strength.

Abstract translation: 本发明公开了一种用于印刷电路板的绝缘膜，树脂涂覆铜（RCC），柔性覆铜层压板（FCCL）和使用该绝缘膜制造的印刷电路板。 更具体地，通过使用根据本发明的优选实施方案的印刷电路板用绝缘膜制造的RCC，FCCL和印刷电路板，包括绝缘层的绝缘膜和形成在其上的底漆层 包含苯并环丁烯（BCB）的树脂可以具有低的热膨胀系数和高的剥离强度。

公开(公告)号：US20120178260A1

公开(公告)日：2012-07-12

申请号：US13427184

申请日：2012-03-22

Applicant: Pui-Yan Lin ,  Govindasamy Paramasivam Rejendran ,  George Elias Zahr

Inventor： Pui-Yan Lin ,  Govindasamy Paramasivam Rejendran ,  George Elias Zahr

IPC: H01L21/31

CPC classification number: H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/108 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/2998 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31529 ,  H01L2924/00

Abstract: Provided are processes for making multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film.

Abstract translation: 提供了制造包含不对称交联聚合物电介质膜的多层芯片载体的方法。

公开(公告)号：US20110220722A1

公开(公告)日：2011-09-15

申请号：US12781823

申请日：2010-05-18

Applicant: TAI-CHERNG YU ,  YUNG-LUN HUANG

Inventor： TAI-CHERNG YU ,  YUNG-LUN HUANG

IPC: G06K19/067 ,  B32B37/14

CPC classification number: B32B37/142 ,  B32B2310/0843 ,  B32B2519/02 ,  B82Y10/00 ,  G06K19/07773 ,  G06K19/0779 ,  H05K1/09 ,  H05K3/103 ,  H05K2201/026 ,  H05K2201/0269 ,  H05K2201/0323 ,  H05K2203/0271 ,  H05K2203/107

Abstract: An exemplary radio frequency identification tag antenna includes a substrate and a patterned carbon nanotube layer. The patterned carbon nanotube layer is formed on the substrate. The carbon nanotube layer consists of a number of carbon nanotube segments. The carbon nanotube segments are connected end-to-end and well aligned. Each carbon nanotube segment includes a number of carbon nanotubes substantially parallel to each other.

Abstract translation: 示例性射频识别标签天线包括基板和图案化碳纳米管层。 图案化的碳纳米管层形成在基板上。 碳纳米管层由许多碳纳米管段组成。 碳纳米管片段端对端连接并良好对准。 每个碳纳米管段包括基本上彼此平行的多个碳纳米管。

公开(公告)号：US07846641B2

公开(公告)日：2010-12-07

申请号：US12143446

申请日：2008-06-20

Applicant: Ryohei Satoh ,  Koji Nakagawa ,  Reo Usui ,  Kenji Tanaka ,  Satoru Takaki ,  Kenichi Ebata ,  Yumiko Aoki

Inventor： Ryohei Satoh ,  Koji Nakagawa ,  Reo Usui ,  Kenji Tanaka ,  Satoru Takaki ,  Kenichi Ebata ,  Yumiko Aoki

IPC: G03F7/26

CPC classification number: H05K3/28 ,  H01J9/02 ,  H01J11/12 ,  H01J11/34 ,  H05K1/0306 ,  H05K3/027 ,  H05K3/38 ,  H05K2201/0269 ,  Y10T428/24868

Abstract: A process for producing a glass substrate having a circuit pattern is disclosed. The process includes forming a thin film layer on a glass substrate and then irradiating the thin film layer with laser light to form a circuit pattern on the glass substrate; depositing a low-melting point glass having a softening point of from 450 to 630° C. on the glass substrate having the circuit pattern formed thereon; and sintering the low-melting point glass to form a low-melting point glass layer which includes the low-melting point glass sintered on the glass substrate having the circuit pattern formed thereon and which forms a compatible layer between the glass substrate and the low-melting point glass layer.

Abstract translation: 公开了一种具有电路图案的玻璃基板的制造方法。 该方法包括在玻璃基板上形成薄膜层，然后用激光照射薄膜层，以在玻璃基板上形成电路图案; 在其上形成有电路图案的玻璃基板上沉积软化点为450〜630℃的低熔点玻璃; 并烧结低熔点玻璃以形成低熔点玻璃层，该低熔点玻璃层包括在其上形成有电路图案的玻璃基板上烧结的低熔点玻璃，并且在玻璃基板和低熔点玻璃之间形成相容层， 熔点玻璃层。

公开(公告)号：US07691469B2

公开(公告)日：2010-04-06

申请号：US12049848

申请日：2008-03-17

Applicant: Masato Nomiya

Inventor： Masato Nomiya

IPC: B32B9/00

CPC classification number: H05K3/38 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0269 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942

Abstract: A ceramic multilayer substrate exhibiting reduced pealing and breakage of an internal conductor disposed between a ceramic layer serving as a base member and a ceramic layer for restricting shrinkage includes a first ceramic layer 11, a second ceramic layer 12 laminated so as to come into contact with a principal surface of the first ceramic layer 11, and an internal conductor 13 disposed between the first ceramic layer 11 and the second ceramic layer 12, a phosphorus component layer 16a is disposed in the first ceramic layer 11 with a concentration gradient in which the concentration decreases in a direction away from the internal conductor 13.

Abstract translation: 表现出设置在用作基底的陶瓷层和用于限制收缩的陶瓷层之间的内部导体的减小的剥离和断裂的陶瓷多层基板包括层叠以与第二陶瓷层12接触的第一陶瓷层11，第二陶瓷层12 第一陶瓷层11的主表面和设置在第一陶瓷层11和第二陶瓷层12之间的内部导体13，在第一陶瓷层11中设置磷成分层16a，浓度梯度为浓度梯度， 在远离内部导体13的方向上减小。