公开(公告)号：US20030063225A1

公开(公告)日：2003-04-03

申请号：US10256742

申请日：2002-09-27

Applicant: Alps Electric Co., Ltd.

Inventor： Michinori Sasaki

IPC: H04N005/50

CPC classification number: H05K1/116 ,  H04N5/64 ,  H05K1/0295 ,  H05K3/3447 ,  H05K2201/09954 ,  H05K2201/10696

Abstract: A video-apparatus-tuner mounting board includes a television tuner mounted on the board; a predetermined circuit to be connected to pins connected to an internal circuit of the television tuner; through holes arranged in a line, into which pins are inserted; and conductor lands, formed around the through holes, to be connected to the pins. Of the conductor lands, first conductor lands connected to the pins of a specific television tuner to be mounted on the board are connected to the predetermined circuit and to second conductor lands, which are not connected to the pins of the specific television tuner.

Abstract translation: 视频装置调谐器安装板包括安装在电路板上的电视调谐器; 要连接到连接到电视调谐器的内部电路的引脚的预定电路; 一排排成一排的通孔，销插入该通孔中; 并且形成在通孔周围的导体平台连接到销。 在导体焊盘中，连接到要安装在板上的特定电视调谐器的引脚的第一导体焊盘连接到预定电路和未连接到特定电视调谐器的引脚的第二导体焊盘。

公开(公告)号：US6115254A

公开(公告)日：2000-09-05

申请号：US441525

申请日：1999-11-16

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H01L23/367 ,  H01L23/433 ,  H05K1/02 ,  H05K3/30 ,  H05K7/20

CPC classification number: H05K3/303 ,  H01L23/3675 ,  H01L23/4334 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10659 ,  H05K2201/10696 ,  Y02P70/613

Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.

公开(公告)号：US5861669A

公开(公告)日：1999-01-19

申请号：US488673

申请日：1995-06-07

Applicant: Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

Inventor： Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

IPC: H01L23/482 ,  H01L23/495 ,  H01L23/58 ,  H05K3/30 ,  H05K3/34 ,  H01L29/41

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.

Abstract translation: 具有单列直插式封装的半导体器件包括：半导体芯片;封装体，其容纳半导体芯片并由一对相对的主表面限定;多个互连引线，其由所述封装主体保持，以基本上延伸 垂直于底面。 每个互连引线由位于封装主体内部的内引线部分和位于封装主体外部的外引线部分组成，外引线部分在内部与外部之间的边界处侧向弯曲，在第一 以及彼此相对并且基本上垂直于包装主体的相对主表面的第二方向。 多个支撑腿在包装体的底表面处横向延伸，用于当将半导体器件放置在基底上时支撑包装体直立。

公开(公告)号：US5773321A

公开(公告)日：1998-06-30

申请号：US766874

申请日：1996-12-13

Applicant: Toshimitsu Ishikawa ,  Atsushi Kitamura ,  Kenji Hirayama

Inventor： Toshimitsu Ishikawa ,  Atsushi Kitamura ,  Kenji Hirayama

IPC: H05K13/04 ,  H01L23/31 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H01L21/60

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H05K1/181 ,  H05K3/303 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/0002 ,  H05K2201/10454 ,  H05K2201/1053 ,  H05K2201/10537 ,  H05K2201/10696 ,  H05K3/3421 ,  Y02P70/611 ,  Y02P70/613

Abstract: A method of counting semiconductor integrated circuit devices comprising steps of forming a semiconductor device block having a plurality of semiconductor integrated circuit devices of vertical mounting type coupled to each other in parallel, and mounting the semiconductor device block on a printed board. A block of semiconductor integrated circuit devices comprising a plurality of semiconductor integrated circuit devices of vertical mounting type, and coupling means for coupling the plurality of semiconductor integrated circuit devices each other in parallel.

Abstract translation: 一种计数半导体集成电路器件的方法，包括以下步骤：形成半导体器件块，所述半导体器件块具有并联连接的多个垂直安装型半导体集成电路器件，并将半导体器件块安装在印刷电路板上。 一种半导体集成电路器件，包括垂直安装型的多个半导体集成电路器件，以及用于将多个半导体集成电路器件并联连接的耦合器件。

公开(公告)号：US5621619A

公开(公告)日：1997-04-15

申请号：US445237

申请日：1995-05-19

Applicant: Lewis L. Seffernick ,  Neal F. Thomas

Inventor： Lewis L. Seffernick ,  Neal F. Thomas

IPC: H01C1/01 ,  H01C13/02 ,  H01C17/00 ,  H01C17/28 ,  H05K3/30 ,  H05K3/34 ,  H01R9/00

CPC classification number: H05K3/303 ,  H01C13/02 ,  H01C17/006 ,  H05K3/3442 ,  H05K2201/09909 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2201/10984 ,  H05K2203/167 ,  H05K3/3452 ,  Y02P70/613

Abstract: A resistor network is disclosed which is suited for surface mount which does not incorporate wire terminations. The network is fabricated entirely from cermet, ceramic, and solder, yet will absorb thermal stresses normally associated with circuitry energization when properly mounted upon a substrate. This is accomplished by controlling the formation of solder bumps and simultaneously controlling the mounted distance between those bumps and a wiring substrate upon which the network is mounted. Additionally, the network may be formed to be either a SIP or DIP configuration, depending upon whether an additional groove is incorporated into the termination side of the substrate. Two alternative embodiments are also disclosed which incorporate various features of the invention.

Abstract translation: 公开了一种适用于不包含电线终端的表面安装的电阻器网络。 网络完全由金属陶瓷，陶瓷和焊料制成，但是当正确安装在基板上时，它将吸收通常与电路通电相关的热应力。 这是通过控制焊料凸点的形成并同时控制这些凸起之间的安装距离和安装网络的布线基板来实现的。 另外，取决于附加的沟槽是否被结合到衬底的端接侧中，网络可以形成为SIP或DIP配置。 还公开了两个替代实施例，其包括本发明的各种特征。

公开(公告)号：US5574310A

公开(公告)日：1996-11-12

申请号：US485117

申请日：1995-06-07

Applicant: Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

Inventor： Michio Sono ,  Junichi Kasai ,  Masanori Yoshimoto ,  Kazuto Tsuji ,  Kouji Saito

IPC: H01L23/482 ,  H01L23/495 ,  H01L23/58 ,  H05K3/30 ,  H05K3/34 ,  H01L29/41

CPC classification number: H05K3/303 ,  H01L23/49555 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K3/3426 ,  Y02P70/613

Abstract: A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.

Abstract translation: 具有单列直插式封装的半导体器件包括：半导体芯片;封装体，其容纳半导体芯片并由一对相对的主表面限定;多个互连引线，其由所述封装主体保持，以基本上延伸 垂直于底面。 每个互连引线由位于封装主体内部的内引线部分和位于封装主体外部的外引线部分组成，外引线部分在内部与外部之间的边界处侧向弯曲，在第一 以及彼此相对并且基本上垂直于包装主体的相对主表面的第二方向。 多个支撑腿在包装体的底表面处横向延伸，用于当将半导体器件放置在基底上时支撑包装体直立。

公开(公告)号：US5446317A

公开(公告)日：1995-08-29

申请号：US26809

申请日：1993-03-05

Applicant: Mitsutaka Sato ,  Masanori Yoshimoto

Inventor： Mitsutaka Sato ,  Masanori Yoshimoto

IPC: H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18 ,  H05K3/30 ,  H01L23/48 ,  H05K7/00 ,  H01L29/44 ,  H01L29/52

CPC classification number: H01L23/3107 ,  H01L23/49555 ,  H01L25/105 ,  H05K3/301 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K1/181 ,  H05K2201/10454 ,  H05K2201/10606 ,  H05K2201/10696

Abstract: A semiconductor package of a single in-line type including a semiconductor chip, a package body for accommodating the semiconductor chip and a plurality of leads held by the package body to extend substantially perpendicularly to a bottom edge surface of the package body. The package body carries a cutout part at a predetermined position of a side edge that surrounds the package body such that the cutout part is adapted for engagement with a support leg for supporting the package body substantially upright on a substrate.

Abstract translation: 包括半导体芯片，用于容纳半导体芯片的封装主体和由封装主体保持的多个引线的单个在线型半导体封装，其基本上垂直于封装体的底部边缘表面延伸。 包装体在围绕包装主体的侧边缘的预定位置处携带切口部分，使得切口部分适于与用于将包装体基本上直立支撑在基板上的支撑腿接合。

公开(公告)号：US5367192A

公开(公告)日：1994-11-22

申请号：US165043

申请日：1993-12-06

Applicant: Angelo Massironi

Inventor： Angelo Massironi

IPC: H01L23/495 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48 ,  H05K1/08

CPC classification number: H01L23/49548 ,  H05K3/308 ,  H01L2924/0002 ,  H05K2201/09709 ,  H05K2201/10696 ,  H05K2201/10757 ,  H05K2201/10871 ,  H05K3/3447

Abstract: This package for integrated devices, to be fixed on supporting plates, in particular on printed circuits, comprises contact pins to be inserted in holes of the supporting plates and to be soldered thereto. To prevent overturning of the package, which may lead to short circuits among the components, at least some of the contact pins are provided with protruding portions defining abutments cooperating with the supporting plate to limit the inclination of the package with respect to the plate.

Abstract translation: 用于固定在支撑板上，特别是印刷电路上的集成器件的封装包括插入支撑板的孔中并被焊接到其上的接触针。 为了防止包装翻倒，这可能导致部件之间的短路，至少一些接触销设置有突出部分，突出部分限定与支撑板配合的支座，以限制包装相对于板的倾斜度。

公开(公告)号：US3524108A

公开(公告)日：1970-08-11

申请号：US3524108D

申请日：1967-12-26

Applicant: CTS CORP

Inventor： ENGLISH JACK A

IPC: H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K7/06 ,  H05K7/12

CPC classification number: H05K3/306 ,  H05K3/308 ,  H05K3/32 ,  H05K3/3447 ,  H05K2201/09827 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/10568 ,  H05K2201/10696 ,  H05K2201/10757 ,  H05K2201/10863 ,  H05K2201/10878 ,  H05K2201/2036

公开(公告)号：KR100201168B1

公开(公告)日：1999-06-15

申请号：KR1019950022303

申请日：1995-07-22

Applicant: 미쓰비시덴키 가부시키가이샤

Inventor： 우에다테쓰야

IPC: H01L23/04

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/03 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/303 ,  H05K3/3426 ,  H05K2201/09709 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: For a device (1) configured for surface mounting the IC (2), connecting pads (3), and the interconnecting leads (4) joined to the pads are all within the surface of the resin (6) with only the solder bumps (5) that are connected to the leads (4) showing through the surface of the mould. The resin encapsulation may also be used for devices configured for bump-grid array (BGA), zig=zag or ZIP, SVP or other PCB mounting methods, in each case only the appropriate device supports and connectors being accessible outside the resin mould for reflow soldering to the PCB surface. The method may also be used with TAB IC's.