公开(公告)号：JPH06132538A

公开(公告)日：1994-05-13

申请号：JP32551992

申请日：1992-12-04

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  ZAMBRANO RAFFAELE

IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L29/784

Abstract: PURPOSE: To allow a dynamic insulating circuit-equipped control circuit of a semiconductor electronic device to reliably keep the semiconductor electronic device insulated even in a negatively charged transient state. CONSTITUTION: A switch S1 connects an insulating region to a ground. A switch S2 connects the insulating region to a collector or drain of a power transistor. A switch S3 connects the insulating region to a control circuit transistor region. A dynamic insulating circuit of a control circuit is constructed of a driving circuit CPI. Such dynamic insulating circuit closes the switch S1 when the potential of the ground or insulating region is lower than the voltage of the collector or drain of the power transistor or the potential of the control circuit region, closes the switch S2 and opens the switch S1 simultaneously when the voltage of the collector or drain of the power transistor is lower than the potential of the ground or insulating region, and closes the switch S3 and opens the switch S1 simultaneously when the potential of the control circuit region is lower than the potential of the ground or insulating region.

公开(公告)号：JPH065789A

公开(公告)日：1994-01-14

申请号：JP11378891

申请日：1991-04-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAEERE TSUANBURAANO

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To optimize current capacity, serial drain resistance and operating voltage of a power stage by providing one or more regions of formed high dopant density, after growing a first epitaxial layer. CONSTITUTION: This method for forming embedded drain or collector region comprises the steps for growing a same conductivity-type first epitaxial layer 2 as that of a substrate 1. The layer 2 has a high density dopant, having lower diffusion coefficient with the same conductivity type as that of the substrate 1 therein. The method further comprises the steps of forming at least one region for constituting an embedded drain region 3 or collector region of a power transistor designed to be connected to the substrate 1. Thus, a boundary between the epitaxial region and the diffused collector region is clarified, and in the case of the series drain resistance or bipolar power transistor, there is no adverse effects on current capacity.

公开(公告)号：JPH05252006A

公开(公告)日：1993-09-28

申请号：JP19823192

申请日：1992-07-24

Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

Inventor： ZISA MICHELE ,  BELLUSO MASSIMILIANO ,  PAPARO MARIO

IPC: H03F3/217 ,  H03K4/58 ,  H03K5/02 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017

Abstract: PURPOSE: To actualize the bootstrap circuit which drives a power MOS transistor(TR) with high-potential side constitution wherein the power MOS TR is able to operate with a low-level supply voltage when operating at a high switching frequency. CONSTITUTION: The bootstrap circuit for the power MOS TR of the high- potential side driving constitution includes a 1st capacitor C1 which can be charged to a 1st voltage level of the supply voltage of the power TR T1. A 2nd capacitor C2 is provided in combination with the 1st capacitor C1 so that a 1st voltage and a 2nd voltage higher than the threshold voltage of the power TR T1 can be used.

公开(公告)号：JPH05121678A

公开(公告)日：1993-05-18

申请号：JP9665392

申请日：1992-04-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAEERE ZANBURAANO

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73

Abstract: PURPOSE: To provide a monolithic semiconductor device which can thin a separation region and suitably adjust the dopant distribution, and which improves the price and productivity. CONSTITUTION: A base region 30 of a power transistor and a horizontal separation region 31 of an integrated control circuit or a collector region 32 of an integrated control circuit are grown sequentially on a lower epitaxial layer 2, which is a second conductivity type, opposite to a first conductivity type, and a part of an epitaxial layer 3 of the first conductivity type constitutes them.

公开(公告)号：JPH09284063A

公开(公告)日：1997-10-31

申请号：JP12961996

申请日：1996-05-24

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MERUKIOTSURE BURUTSUKOREERI ,  GAETAANO KOSENCHIINO ,  MARUKO DEMICHIERI ,  JIUSETSUPE PATSUTEI

IPC: G05F3/22 ,  G05F3/26 ,  H03F3/343 ,  H03K17/04 ,  H03K17/60

Abstract: PROBLEM TO BE SOLVED: To provide the current generator stage for integrated analog circuit in which a power-down time and a power-up time are considerably reduced. SOLUTION: A current generator stage 1 of a type having a current source 2 inserted between a 1st reference power supply voltage Vdd and, a 1st fixed reference voltage GND is provided with a at least one current mirror circuit 5 connecting to a current source 2 to produce at least one output current and a bias circuit 10 connecting to the current source 2 to apply a bias voltage to the current source. The bias circuit 10 of the current generator stage 1 has an energy storage circuit 11, and the energy storage circuit 11 is in the 1st circuit mode indicating a combination of a 1st reactance X1 and a 2nd reactance X2 when the current source 2 is set in the 1st operating mode and in the 2nd circuit mode to apply a prescribed bias voltage to the current source 2 when the current source 2 is in the 2nd operation mode.

公开(公告)号：JPH09186328A

公开(公告)日：1997-07-15

申请号：JP35056296

申请日：1996-12-27

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ANTONIO GURIMARUDEI ,  ANTONIINO SHIRATSUCHI ,  FUERUCHIO FURISHINA ,  JIYUSETSUPE FUERURA

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS gate power device having low gate resistance, improved dynamic performance and high frequency performance. SOLUTION: A MOS gate power device contains a P-type web structure formed on an N semiconductor layer 2. The P-type web structure contains a P-type annular frame part 6 arranged on the N semiconductor layer 2 surrounding a plurality of P-type body parts 9, and a P-type long and narrow strip 6 extended to the direction almost crossing at right angle with the P-type body parts 9. The end part of the P-type long and narrow strip 6 is incorporated with the P-type annular frame part.

公开(公告)号：JPH09167955A

公开(公告)日：1997-06-24

申请号：JP12966396

申请日：1996-05-24

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： GOLA ALBERTO ,  LEONE VIA TERRAZZANO ,  FUCILI GIONA ,  MILAZZO PATRIZIA

IPC: H03K17/00 ,  H03K17/082 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To provide the detection and protection circuit for occurrence of a short-circuit for a digital output stage. SOLUTION: The detection and protection circuit for occurrence of a short- circuit for a digital output stage is provided and the circuit has an exclusive OR logic gate circuit EX1 with a 1st input terminal connecting to a signal input circuit (IN) and an output terminal connecting to an input terminal of a signal level shifter B. An exclusive OR 2nd logic gate circuit EX2 has a 1st input terminal connecting to the input node IN and a 2nd input terminal connecting to an output terminal OUT of the output stage B via an inverter circuit INI. A 2nd input terminal of the 1st logic gate circuit is connected to an output terminal of the 2nd logic gate circuit via a comparator circuit SCH1 and delay circuit means consisting of C, R, D.

公开(公告)号：JPH0923020A

公开(公告)日：1997-01-21

申请号：JP3999796

申请日：1996-02-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： PIERO JIYORUJIYO FUATSURIKA

IPC: G01T1/24 ,  H01L31/09 ,  H01L31/115 ,  H01L31/118

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor particle detector which has such a structure that is suitable for large-scale production and can work as a position detector also. SOLUTION: A particle detector is formed of a semiconductor substrate 20 composed of first and second layers 22 and 23 of a first conductivity (N), a third layer 21 of a second conductivity (P) interposed between the first and second layers 22 and 23, first and second means 25 and 31 and 26 and 32 which are respectively arranged on the surfaces of the first and second layers 22 and 23 on the opposite side of their joint surfaces with the third layer 21 and electrically connected to the first and second layers 22 and 23, and means 27 and 24 which are electrically connected to the third layer 23. In order to manufacture the detector in a large industrial scale, the means which are electrically connected to the third layer 23 are composed of a region 24 of the second conductivity (P) extended to the front layer 23 from the front face of the substrate 20 and a means 27 the surface of which is electrically brought into contact with the region 24.

公开(公告)号：JPH08304480A

公开(公告)日：1996-11-22

申请号：JP10553396

申请日：1996-04-25

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： SERUJIO PARAARA ,  SUTEFUANO SUEERI ,  SARUBUATOORE SUKATSUCHIANOOCHI

IPC: G01R19/165 ,  F02P17/12 ,  G01R29/027 ,  H01T13/60 ,  H02H3/08 ,  H02H3/20

Abstract: PROBLEM TO BE SOLVED: To detect an overload of an electric load inserted between a feeder line and a control switch accurately by providing a feedback block, being inserted along with input and output terminals, between the output terminal of a circuit and the input terminal of a following logic block. SOLUTION: A circuit 1 detects an overload of an electric load Z1 inserted between a feeder line AL and a control switch S and includes a feedback block R, being inserted along with input and output terminals, between the output terminal OUT and the input of a following logic block D. The block D also includes an OR type logic gate P1 and an AND type logic gate P2 and the block R also includes a reference voltage E3 and a threshold comparator C3. It is controlled by the block D having inputs connected with the output terminals of threshold comparators C1, C2 of an output transistor T1. Peak value of the voltage Va is about 400V when the spark is not present and about 250V when the spark is present.

公开(公告)号：JPH08293606A

公开(公告)日：1996-11-05

申请号：JP3651496

申请日：1996-02-23

Applicant: CONS RIC MICROELETTRONICA

Inventor： ANTONIO GURIMARUDEI ,  ANTONIINO SHIIRATSUCHI

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve a dynamic characteristic without sacrificing a normal state characteristic by interdigitating elongated stripes, plural source metal fingers which are brought into contact with an elongated source region and conductive gate fingers. SOLUTION: An elongated doped semiconductor stripes 11 of a first conductivity type formed in a semiconductor layer of a second conductivity type is provided. The elongated stripes 11 contain the elongated source regions of the first conductivity type and they are provided with the first conductive annular doped semiconductor regions 8 which are formed in the semiconductor layer, surround the elongated stripes 11 and are merged with the stripes. Furthermore, insulating gate stripes 16 extending on the semiconductor layer between the adjacent elongated stripes 11, conductive gate fingers 4 which extend on the insulating gate stripes 16 and which are electrically connected with the stripes and source metal fingers 7 which are brought into contact with the long stripes 11 and the elongated source regions 15 are provided. Thus, the fingers 7 and 4 are interdigitated.