公开(公告)号：EP4478112A1

公开(公告)日：2024-12-18

申请号：EP23215720.6

申请日：2023-12-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： RAKOWSKI, Michal ,  CHANDRAN, Sujith ,  HIROKAWA, Takako ,  GONZALEZ, Pilar

IPC: G02F1/01 ,  G02F1/025 ,  G02F1/21 ,  G02F1/225 ,  G02F1/313

Abstract: Structures for a broadband optical switch and methods of forming such structures. The structure comprises a Mach-Zehnder interferometer including first and second arms. The first arm comprises a first waveguide core, and the second arm comprises a second waveguide core. The structure further comprises a ring resonator comprising a third waveguide core that has a first thickness. A portion of the third waveguide core is adjacent to a portion of the first waveguide core over a light coupling region. A slab layer connects the portion of the first waveguide core to the portion of the third waveguide core. The slab layer has a second thickness that is less than the first thickness of the first waveguide core.

公开(公告)号：EP4439678A1

公开(公告)日：2024-10-02

申请号：EP23198447.7

申请日：2023-09-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Melde, Thomas ,  Richter, Ralf ,  Dünkel, Stefan

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/402 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66628 ,  H01L29/42368

Abstract: Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

公开(公告)号：EP4428924A1

公开(公告)日：2024-09-11

申请号：EP24152505.4

申请日：2024-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： PANDEY, Shesh Mani ,  KARALKAR, Sagar Premnath ,  KRISHNASAMY, Rajendran ,  NATH, Anindya

IPC: H01L29/06 ,  H01L21/329 ,  H01L29/87

CPC classification number: H01L29/0649 ,  H01L29/87 ,  H01L29/66121

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and a deep trench isolation structure between the plurality of shallow trench isolation structures and extending into the semiconductor material deeper than the plurality of shallow trench isolation structures.

公开(公告)号：EP4354443A3

公开(公告)日：2024-08-21

申请号：EP23187997.4

申请日：2023-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC: G11C29/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/54 ,  G11C11/16

CPC classification number: G11C29/028 ,  G11C13/004 ,  G11C11/1673 ,  G11C2013/005420130101 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0004 ,  G11C11/54 ,  G11C11/161 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/12

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

公开(公告)号：EP4411823A1

公开(公告)日：2024-08-07

申请号：EP23206305.7

申请日：2023-10-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： HEBERT, Francois

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/0623 ,  H01L29/66734 ,  H01L29/1608 ,  H01L29/66068

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer in the trench, and a dielectric layer on the top surface of the semiconductor substrate. The dielectric layer includes an opening that is aligned with the trench in the semiconductor substrate, and the dielectric layer comprises a material with a melting point that is greater than or equal to 2000°C.

公开(公告)号：EP4407687A1

公开(公告)日：2024-07-31

申请号：EP23197357.9

申请日：2023-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Holt, Judson Robert ,  Mulfinger, George Robert

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78684 ,  H01L29/42384

Abstract: An integrated circuit (IC) device is disclosed which includes a first transistor over a substrate. The first transistor includes a gate over the substrate and between a source region and a drain region. The transistor further includes a first region of vertically-graded silicon germanium ("SiGe") adjacent a first side of a channel under the gate, and a second region of vertically-graded SiGe adjacent a second side of the channel. The channel includes substantially uniformly-graded SiGe.

公开(公告)号：EP4404270A1

公开(公告)日：2024-07-24

申请号：EP23205075.7

申请日：2023-10-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： HEBERT, Francois

IPC: H01L29/06 ,  H01L21/283 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/66037 ,  H01L29/1608 ,  H01L29/0623 ,  H01L29/66719 ,  H01L29/66734 ,  H01L21/28518

Abstract: Structures for a field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer. The gate conductor layer has a first portion disposed above the top surface of the semiconductor substrate and a second portion disposed inside the trench below the top surface of the semiconductor substrate.

公开(公告)号：EP4401123A1

公开(公告)日：2024-07-17

申请号：EP23211353.0

申请日：2023-11-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： ETHIRAJAN, Tamilmani ,  SHANBHAG, Kaustubh ,  MULFINGER, George R. ,  TOKRANOV, Anton V. ,  KOZARSKY, Eric S. ,  ZHAN, Hui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78 ,  H01L29/0653 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7848 ,  H01L29/165 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with isolation structures in active regions and methods of manufacture. The structure includes: an active region; a plurality of isolation structures (14) within the active region; a plurality of gate structures (16) overlapping the plurality of isolation structures within the active region; and diffusion regions on sides of the plurality of gate structures and the plurality of isolation structures.

公开(公告)号：EP4400883A2

公开(公告)日：2024-07-17

申请号：EP23205378.5

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng

IPC: G02B6/125

CPC classification number: G02B2006/1214720130101 ,  G02B6/125

Abstract: Structures for a directional coupler and methods of forming a structure for a directional coupler. The structure comprises a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments disposed adjacent to the first plurality of segments in a coupling region. The structure further comprises a first cladding layer comprising a first material that has a first refractive index, and a second cladding layer comprising a second material that has a second refractive index different from the first refractive index. The first cladding layer adjoins a first sidewall of each of the first plurality of segments and a first sidewall of each of the second plurality of segments, and the second cladding layer adjoins a second sidewall of each of the first plurality of segments and a second sidewall of each of the second plurality of segments.

公开(公告)号：EP4398701A1

公开(公告)日：2024-07-10

申请号：EP23195307.6

申请日：2023-09-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pritchard, David ,  Yu, Hong ,  Zhao, Zhixing

IPC: H10N97/00

CPC classification number: H01L28/91

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.