公开(公告)号：KR2019970009767U

公开(公告)日：1997-03-29

申请号：KR2019950022870

申请日：1995-08-29

Applicant: 삼성전자주식회사

Inventor： 조민수

IPC: D06F17/00

公开(公告)号：KR1020160133599A

公开(公告)日：2016-11-23

申请号：KR1020150065993

申请日：2015-05-12

Applicant: 삼성전자주식회사

Inventor： 노미야마,타카히로 ,  손일영 ,  이수호 ,  조민수 ,  한재열

IPC: H02M3/155

CPC classification number: H02M3/158 ,  H02M2001/0025 ,  H02M2003/1566 ,  H03K5/24

Abstract: 본발명에따른전원변환장치는전압변환부, 피드백회로부, 구동신호생성부, 천이상태탐지부, 및저항값조절부를포함한다. 전압변환부는입력전압을제공받아구동신호에응답하여입력전압의전압레벨을변경하여출력전압으로출력한다. 피드백회로부는상기출력전압을전압분배하기위한피드백저항들을포함하며, 상기분배된출력전압을피드백전압으로출력한다. 구동신호생성부는상기피드백전압의레벨과기준전압의레벨을비교하여상기구동신호를출력한다. 천이상태탐지부는상기피드백전압의레벨과상기기준전압의레벨을비교하여상기출력전압의천이상태에대응하는천이상태신호를출력한다. 저항값조절부는상기천이상태신호에응답하여상기피드백저항들의저항값을변경한다.

Abstract translation: 电力转换电路包括电压转换电路，反馈电路，驱动信号发生器，瞬态状态检测器和电阻值调节器。 电压转换电路响应于驱动信号改变输入电压的电压电平，并且根据输入电压的改变的电压电平输出输出电压。 反馈电路分压输出电压，将分压输出电压输出为反馈电压。 驱动信号发生器将反馈电压的电平与参考电压的电平进行比较，并输出驱动信号。 瞬态状态检测器将反馈电压的电平与参考电压的电平进行比较，并输出与输出电压的过渡状态对应的瞬态状态信号。 电阻值调节器根据瞬态状态信号调整反馈电阻值，该值反映输出电压。

公开(公告)号：KR1020160040839A

公开(公告)日：2016-04-15

申请号：KR1020140134256

申请日：2014-10-06

Applicant: 삼성전자주식회사

Inventor： 조민수 ,  한재열 ,  금동진 ,  손일영 ,  쿠도

IPC: H02M3/155 ,  G05F1/56

CPC classification number: H02M3/1582 ,  H02M3/1563

Abstract: 벅-부스트컨버터는컨버팅회로, 리플인젝터, 히스테리시스비교기및 스위칭컨트롤러를포함한다. 컨버팅회로는벅 모드에서입력전압을강압하여제 1 출력전압을생성하고, 부스트모드에서입력전압을승압하여제 3 출력전압을생성하며, 벅-부스트모드에서입력전압을강압또는승압하여제 1 출력전압과제 3 출력전압사이의제 2 출력전압을생성한다. 리플인젝터는벅 모드, 벅-부스트모드및 부스트모드각각에서컨버팅회로내부의스위칭동작에상응하는스위칭신호에기초하여교류전압에상응하는리플을생성한다. 히스테리시스비교기는벅 모드, 벅-부스트모드및 부스트모드각각에서제 1 내지제 3 출력전압들각각이전압분배되어생성된감압전압에리플이더해진피드백전압을출력제어전압과비교하여적어도하나이상의스위칭제어신호를출력한다. 스위칭컨트롤러는스위칭제어신호에기초하여컨버팅회로의전류흐름경로를변경한다.

Abstract translation: 提供了降压 - 升压转换器和包括降压 - 升压转换器的功率管理集成电路。 降压 - 升压转换器包括：转换电路; 波纹注射器 磁滞比较器; 和开关控制器。 转换电路通过在降压模式下降低输入电压，通过在升压模式下升压输入电压，通过升压或降压输入电压降压第二输出电压来产生第一输出电压 升压模式，其中第二输出电压具有在第一输出电压的电压电平和第三输出电压的电压电平之间的电压电平。 纹波注入器基于与降压模式，降压 - 升压模式和升压模式中的转换电路的切换操作相对应的开关信号，产生对应于交流电压的纹波。 迟滞比较器基于输出控制电压和反馈电压之间的比较来输出至少一个开关控制信号，所述反馈电压是通过将纹波加到通过在降压模式中对第一输出电压进行分压而产生的分压而产生的，执行 在降压 - 升压模式下对第二输出电压进行分压，并且在升压模式下对第三输出电压进行分压。 切换控制器基于切换控制信号改变转换电路的电流流动路径。

公开(公告)号：KR1020110041309A

公开(公告)日：2011-04-21

申请号：KR1020090098408

申请日：2009-10-15

Applicant: 삼성전자주식회사

Inventor： 조민수

IPC: H03K19/0185

CPC classification number: G06F1/26 ,  H03K3/356113

Abstract: PURPOSE: A negative level shifter is provided to change the voltage level of an input signal by using a level shifting circuit of one stage. CONSTITUTION: A voltage selector(110) applies a first voltage to a first node and a second voltage to a second node at a first section in response to a control signal. The voltage selector applies a third voltage to the first node and a fourth voltage to a second node at a second section. At least one voltage level converter(150) is connected to the first node and the second node. The voltage level converter converts the voltage level of the input signal by using the voltages of the first and second nodes.

Abstract translation: 目的：提供一个负电平转换器，通过使用一级的电平转换电路来改变输入信号的电压电平。 构成：响应于控制信号，电压选择器（110）将第一电压施加到第一节点并且将第二电压施加到第一部分处的第二节点。 电压选择器将第三电压施加到第一节点，并将第四电压施加到第二节点处的第二节点。 至少一个电压电平转换器（150）连接到第一节点和第二节点。 电压电平转换器通过使用第一和第二节点的电压来转换输入信号的电压电平。

公开(公告)号：KR1020070081718A

公开(公告)日：2007-08-17

申请号：KR1020060013887

申请日：2006-02-13

Applicant: 삼성전자주식회사

Inventor： 김순오 ,  이승건 ,  김정민 ,  박연수 ,  조민수

IPC: H01L21/304

Abstract: An apparatus for cleaning a semiconductor substrate is provided to supply uniformly a cleaning solution onto the entire surface of the substrate by spraying the solution toward the substrate from an upper center portion of the substrate. A cleaning apparatus includes a bath(310) for cleaning a substrate, and a spraying part(330) positioned over the substrate which is located in the bath during the cleaning process, to spray a cleaning solution onto the substrate. The spray part is moved out of the bath by a transfer unit(340), so that a support member holding plural substrates comes in or goes out of the bath. The spray part has supply tubes(332) supplying the cleaning solution, spray tubes(334), and spray nozzles each installed on the spray tubes.

Abstract translation: 提供了一种用于清洁半导体衬底的设备，用于通过从衬底的上部中心部分向衬底喷射溶液来均匀地将清洁溶液提供到衬底的整个表面上。 清洁装置包括用于清洁基底的浴（310）和位于清洁过程中位于浴中的基底上的喷射部分（330），以将清洁溶液喷射到基底上。 通过转移单元（340）将喷射部件移出浴液，从而保持多个基板的支撑部件进入或流出浴室。 喷射部分具有供应清洁溶液的供应管（332），喷射管（334）和各自安装在喷射管上的喷嘴。

公开(公告)号：KR100455379B1

公开(公告)日：2004-11-06

申请号：KR1020020009323

申请日：2002-02-21

Applicant: 삼성전자주식회사

Inventor： 조민수 ,  박상욱 ,  김대근

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

Abstract: In a method for manufacturing a flash memory device, a first gate insulating film, a first gate conductive film, and a second insulating film are sequentially formed on a semiconductor substrate. A region where a first gate is to be formed is defined by etching the second insulating film to expose an upper portion of the first gate conductive film. Second conductive film spacers are formed along sidewalls of the etched second insulating film. An oxide film is formed on the exposed surface of the second conductive film spacers and the first gate conductive film. Silicon insulating spacers are formed on the sidewalls of the etched second insulating film. A source junction contact hole is formed by etching the first gate conductive film and the first gate insulating film by using the second insulating film and the silicon insulating film spacers as a mask. A source junction contact fill is formed filling the source junction contact hole. The first gate is formed by sequentially removing the second insulating film and the first gate conductive film.

Abstract translation: 在用于制造闪存器件的方法中，在半导体衬底上顺序地形成第一栅极绝缘膜，第一栅极导电膜和第二绝缘膜。 通过蚀刻第二绝缘膜以暴露第一栅极导电膜的上部来限定将要形成第一栅极的区域。 沿蚀刻的第二绝缘膜的侧壁形成第二导电膜间隔物。 在第二导电膜间隔物和第一栅极导电膜的暴露表面上形成氧化物膜。 硅绝缘间隔物形成在蚀刻的第二绝缘膜的侧壁上。 通过使用第二绝缘膜和硅绝缘膜间隔物作为掩模来蚀刻第一栅极导电膜和第一栅极绝缘膜来形成源极接触孔。 形成填充源接点接触孔的源结接触填充物。 第一栅极通过依次去除第二绝缘膜和第一栅极导电膜而形成。

公开(公告)号：KR100442090B1

公开(公告)日：2004-07-27

申请号：KR1020020017090

申请日：2002-03-28

Applicant: 삼성전자주식회사

Inventor： 김진우 ,  김동준 ,  조민수 ,  김대근

IPC: G11C16/06

CPC classification number: H01L27/11556 ,  H01L27/115

Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

Abstract translation: 提供了具有分裂栅极结构的非易失性存储单元及其制造方法。 非易失性存储器单元包括限定在半导体衬底的预定区域处的有源区。 蚀刻每个有源区的一部分以形成单元沟槽区。 绝缘的浮动栅极设置在平行于与有源区交叉的方向的一对侧壁上。 源区设置在单元沟槽区的底表面处。 浮置栅极之间的间隙区域填充有与源极区域电连接的公共源极线。 公共源极线沿着跨越有源区域的方向延伸。 与浮置栅极相邻的有源区域被与公共源极线平行的字线覆盖。 漏极区域设置在与字线相邻的有源区域中。 漏极区域电连接到跨过字线的位线。

公开(公告)号：KR100435261B1

公开(公告)日：2004-06-11

申请号：KR1020020046499

申请日：2002-08-07

Applicant: 삼성전자주식회사

Inventor： 권철순 ,  유재민 ,  김진우 ,  박재현 ,  김용희 ,  이돈우 ,  김대근 ,  박상욱 ,  김주찬 ,  김국민 ,  조민수 ,  류의열

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line.

Abstract translation: 制造分栅快闪存储器件的方法包括以下步骤：（a）提供导电类型与第一结区的导电类型相反的半导体衬底; （b）在衬底的整个上表面上顺序地形成第一电介质膜，第一导电膜，第二电介质膜和第三电介质膜; （c）将第三电介质膜蚀刻一定的厚度以暴露第二电介质膜; （d）去除暴露的第二介电膜，并去除剩余的第三介电膜; （e）将所述第一导电膜和所述第二电介质膜蚀刻预定的厚度，以部分暴露所述第一导电线和所述第一导电膜; （f）在暴露的第一导线和第一导电膜的一部分上形成第四介电膜; （g）除去剩余的第二电介质膜，并暴露设置在其下部的第一导电膜; （h）使用第四电介质膜作为蚀刻掩模，蚀刻通过去除第二电介质膜而暴露的第一电介质膜和第一导电膜，以及形成第二栅极电介质膜和字线。

公开(公告)号：KR100395769B1

公开(公告)日：2003-08-21

申请号：KR1020010035424

申请日：2001-06-21

Applicant: 삼성전자주식회사

Inventor： 이용규 ,  김동준 ,  조민수 ,  류의열 ,  김진호

IPC: G11C16/14

CPC classification number: G11C16/14

Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Abstract translation: 一种用于在存储单元中执行擦除操作的方法。 将第一电压和第二电压分别施加到源极和漏极区达预定的擦除时间; 并且第一和第二电压在源极区和漏极区之间彼此切换擦除时间至少一次。 由此，容易将空穴注入到源极区和漏极区以及沟道侧表面，并且存储均匀且高速的擦除操作。

公开(公告)号：KR1020030048232A

公开(公告)日：2003-06-19

申请号：KR1020010078105

申请日：2001-12-11

Applicant: 삼성전자주식회사

Inventor： 윤병문 ,  김경현 ,  박정훈 ,  조민수 ,  김동환

IPC: H01L21/8247

Abstract: PURPOSE: A method for forming a tunnel oxide layer of a nonvolatile semiconductor memory device is provided to be capable of increasing coupling ratio by reducing the surface of the tunnel oxide layer. CONSTITUTION: A gate oxide layer(22) is formed on a semiconductor substrate(20). A photoresist pattern is formed on the gate oxide layer(22) for exposing the predetermined portion of the gate oxide layer(22). A sacrificial oxide layer is formed on the resultant structure. An opening portion is formed in the gate oxide layer(22) by carrying out a wet etching process using the photoresist pattern as a mask. A tunnel oxide layer(28) is formed in the bottom portion of the opening portion. Preferably, the sacrificial oxide layer is formed by carrying out a CVD(Chemical Vapor Deposition) process at the temperature of 150-200 °C.

Abstract translation: 目的：提供一种用于形成非易失性半导体存储器件的隧道氧化物层的方法，通过减小隧道氧化物层的表面，能够提高耦合比。 构成：在半导体衬底（20）上形成栅氧化层（22）。 在栅极氧化物层（22）上形成用于暴露栅极氧化物层（22）的预定部分的光刻胶图案。 在所得结构上形成牺牲氧化物层。 通过使用光致抗蚀剂图案作为掩模进行湿式蚀刻工艺，在栅极氧化物层（22）中形成开口部。 隧道氧化物层（28）形成在开口部分的底部。 优选地，牺牲氧化物层通过在150-200℃的温度下进行CVD（化学气相沉积）工艺而形成。