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公开(公告)号：KR101123211B1
公开(公告)日：2012-03-20
申请号：KR1020110006022
申请日：2011-01-20
Applicant: 한국과학기술원
CPC classification number: H03F1/26 , H03F1/223 , H03F1/3205 , H03F1/565 , H03F2200/372 , H03F2200/391 , H03F2200/541 , H04B1/16
Abstract: PURPOSE: A low noise amplifier and a radio receiver are provided to greatly improve linearity by using the body biasing and complementary superposition of a transistor. CONSTITUTION: A low noise amplifier is composed of a complementary common source low noise amplifier(100) linearized. The linearized complementary common source low noise amplifier comprises a first primary transistor part(110), a first subsidiary transistor part(120), and a capacitor(130) for simultaneously matching optimal noise and input impedance. The first primary transistor part comprises a first NMOS(N-Channel Metal Oxide Semiconductor) transistor, a first PMOS(P-Channel Metal Oxide Semiconductor) transistor, and resistance. The first subsidiary transistor part includes a first NMOS transistor of the first primary transistor part and transistors parallely connected to the first PMOS transistor. The capacitor for simultaneous matching is communally connected to output terminals of the first primary transistor part and the first subsidiary transistor part.
Abstract translation: 目的：提供低噪声放大器和无线电接收器，通过使用晶体管的体偏置和互补叠加来大大提高线性度。 构成：低噪声放大器由互补的共源低噪声放大器（100）线性化组成。 线性化互补公共源低噪声放大器包括用于同时匹配最佳噪声和输入阻抗的第一初级晶体管部分（110），第一辅助晶体管部分（120）和电容器（130）。 第一主晶体管部分包括第一NMOS（N沟道金属氧化物半导体）晶体管，第一PMOS（P沟道金属氧化物半导体）晶体管和电阻。 第一辅助晶体管部分包括第一初级晶体管部分的第一NMOS晶体管和并联连接到第一PMOS晶体管的晶体管。 用于同时匹配的电容器共同连接到第一初级晶体管部分和第一辅助晶体管部分的输出端子。
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公开(公告)号：KR1020100027635A
公开(公告)日：2010-03-11
申请号：KR1020080086629
申请日：2008-09-03
Applicant: 한국과학기술원
CPC classification number: H03K23/544 , H03K3/35613 , H03K21/10
Abstract: PURPOSE: A CML type D flip-flop and a frequency odd divider using the same are provided to easily expand a structure by adding the D flip-flops. CONSTITUTION: A first NMOS transistor(NM1) is connected between a first node(N1) and a second node(N2). A second NMOS transistor(NM2) is connected between a third node(N3) and a fourth node(N4). A third NMOS transistor(NM3) is connected between a fifth node(N5) and the second node. A fourth NMOS transistor(NM4) is connected between the fifth node and the fourth node. A fifth NMOS transistor(NM5) is connected between the third node and the fifth node. A sixth NMOS transistor is connected between the first node and the fifth node.
Abstract translation: 目的：提供CML D型触发器和使用其的频率奇数分频器，以通过添加D触发器来容易地扩展结构。 构成：第一NMOS晶体管（NM1）连接在第一节点（N1）和第二节点（N2）之间。 第二NMOS晶体管（NM2）连接在第三节点（N3）和第四节点（N4）之间。 第三NMOS晶体管（NM3）连接在第五节点（N5）和第二节点之间。 第四NMOS晶体管（NM4）连接在第五节点和第四节点之间。 第五NMOS晶体管（NM5）连接在第三节点和第五节点之间。 第六NMOS晶体管连接在第一节点和第五节点之间。
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公开(公告)号：KR1020080048592A
公开(公告)日：2008-06-03
申请号：KR1020060118745
申请日：2006-11-29
CPC classification number: H03G1/0029 , H03F1/0211 , H03F1/223 , H03F1/3205 , H03G1/0023
Abstract: A radio frequency programmable gain amplifier using current amplification is provided to convert an input signal to current and to amplify the converted current by using a common gate amplifier having high linearity. A radio frequency programmable gain amplifier includes a current converter unit(100), a current path unit(110), a current amplifier unit(120), a current amplification ratio control unit(130), and a load(140). The current converter unit converts an input signal to current. The current path unit forms a path for applying the current to the current converter unit. The current amplifier unit amplifies the output current of the current converter unit. The current amplification ratio control unit controls an amplification gain of the current amplifier unit according to an automatic gain control signal. The load supplies the current from a power terminal to the current amplifier unit in order to output an output signal.
Abstract translation: 提供使用电流放大的射频可编程增益放大器，以将输入信号转换为电流，并通过使用具有高线性度的公共栅极放大器来放大转换的电流。 射频可编程增益放大器包括电流转换器单元（100），电流通路单元（110），电流放大器单元（120），电流放大率控制单元（130）和负载（140）。 电流转换器单元将输入信号转换为电流。 电流路径单元形成用于将电流施加到电流转换器单元的路径。 电流放大器单元放大电流转换器单元的输出电流。 电流放大率控制单元根据自动增益控制信号来控制电流放大器单元的放大增益。 负载将电流从电源端子提供给电流放大器单元，以输出输出信号。
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公开(公告)号：KR1020070059451A
公开(公告)日：2007-06-12
申请号：KR1020050118296
申请日：2005-12-06
Applicant: 한국과학기술원
IPC: G11C17/10
CPC classification number: G11C17/12 , G11C5/14 , G11C7/1078 , G11C17/18
Abstract: A circuit apparatus is provided to implement a SOC(System On Chip) through only standard CMOS process by using a CMOS ROM instead of a conventional ROM. A circuit apparatus using a CMOS ROM can be integrated with other devices of the circuit apparatus including a ROM(Read Only Memory) implemented by a standard CMOS(Complementary Metal Oxide Semiconductor) process, through the standard CMOS process. In the ROM, first to third input stages are comprised and data is stored by a voltage applied to the input stages. A cell access transistor includes a gate and a drain forming the second input stage and a source forming the third input stage, and is enabled by a voltage applied between the gate and the source. A high voltage blocking transistor includes a gate, a drain and a source connected to the drain of the cell access transistor, and conducts a current to the source from the drain by a bias voltage applied to the gate, and prevents a high voltage applied to the third input stage from being directly applied to the cell access transistor. An anti-fuse transistor includes a gate forming the third input stage and a source and a drain connected to the drain of the high voltage blocking transistor, and a high voltage is applied to the third input stage, and a gate oxide is broken down when the cell access transistor is enabled.
Abstract translation: 提供了一种电路装置，通过使用CMOS ROM代替常规ROM，仅通过标准CMOS工艺来实现SOC（片上系统）。 使用CMOS ROM的电路装置可以与包括通过标准CMOS工艺的标准CMOS（互补金属氧化物半导体）工艺实现的ROM（只读存储器）的电路装置的其它器件集成。 在ROM中，包括第一至第三输入级，并且通过施加到输入级的电压来存储数据。 电池存取晶体管包括形成第二输入级的栅极和漏极和形成第三输入级的源，并且通过施加在栅极和源极之间的电压使能。 高电压阻断晶体管包括栅极，漏极和连接到电池存取晶体管的漏极的源极，并且通过施加到栅极的偏置电压从漏极导通电流，并且防止施加到栅极 第三输入级被直接应用于单元存取晶体管。 反熔丝晶体管包括形成第三输入级的栅极和连接到高压阻断晶体管的漏极的源极和漏极，并且高电压被施加到第三输入级，并且栅极氧化物被分解为当 单元存取晶体管被使能。
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公开(公告)号：KR100446004B1
公开(公告)日：2004-08-25
申请号：KR1020020040821
申请日：2002-07-12
Applicant: 한국과학기술원
IPC: H04B1/26
CPC classification number: H04B1/30 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D2200/0047
Abstract: This invention is about the direct conversion receiver. It is excellent the receiving sensitivity that DC off-set, matching characteristics of the relationship of I/Q circuits and noise characteristics are improved. In order to achieve this purpose, the direct conversion receiver uses vertical bipolar junction transistor available in standard triple-well CMOS technology in the switching element of mixer and base-band analog circuits. Furthermore, as using the passive mixer in the other practical example of this invention, this invention controls the occurrence of l/f noise. As using the vertical bipolar junction transistor available in standard triple-well CMOS in the base-band analog circuits, this invention realizes the direct conversion receiver that DC off-set, matching characteristics of the relationship of I/Q circuit and noise characteristics are improved.
Abstract translation: 本发明涉及直接转换接收机。 直流偏置，I / Q电路关系的匹配特性和噪声特性得到改善的接收灵敏度非常好。 为了实现这一目的，直接转换接收器在混频器和基带模拟电路的开关元件中使用标准三阱CMOS技术中可用的垂直双极结型晶体管。 而且，在本发明的另一个实际例子中使用无源混频器时，本发明控制了I / f噪声的发生。 由于在基带模拟电路中使用标准三阱CMOS中可用的垂直双极结型晶体管，本发明实现了直流偏移，I / Q电路与噪声特性关系匹配特性得到改善的直接转换接收器 。
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Patent Agency Ranking
公开(公告)号：KR1020040045147A
公开(公告)日：2004-06-01
申请号：KR1020020073181
申请日：2002-11-22
Applicant: 한국과학기술원
IPC: H03F1/08
Abstract: PURPOSE: A high-efficient power amplifier is provided to enhance the efficiency by controlling a bias voltage and changing the load impedance according to each operation level. CONSTITUTION: A high-efficient power amplifier includes an input terminal and an output terminal to amplify a received signal and output the amplified signal. The high-efficient power amplifier further includes a bias control unit and an impedance matching unit. The bias control unit(330) is connected to the input terminal in order to control a bias voltage applied to the input terminal. The impedance matching unit(350) is connected between the output terminal and a load resistance in order to change a load impedance value of the power amplifier. The bias control unit sets up the bias voltage at a back-off point of the power amplifier in a maximum power mode and applies lower voltage than the bias voltage to the power amplifier in a normal mode. The impedance matching unit sets up the load impedance at OP1dB in the maximum power mode and changes the load impedance to the lower impedance than the load impedance in the normal mode.
Abstract translation: 目的：提供高效功率放大器，通过控制偏置电压和根据每个操作级别改变负载阻抗来提高效率。 构成：高效功率放大器包括输入端和输出端，用于放大接收信号并输出放大信号。 高效率功率放大器还包括偏置控制单元和阻抗匹配单元。 偏置控制单元（330）连接到输入端子，以便控制施加到输入端子的偏置电压。 阻抗匹配单元（350）连接在输出端子和负载电阻之间，以便改变功率放大器的负载阻抗值。 偏置控制单元以最大功率模式在功率放大器的退避点处建立偏置电压，并且以正常模式将低于偏置电压的电压施加到功率放大器。 阻抗匹配单元在最大功率模式下将负载阻抗设置在OP1dB，并将负载阻抗改变为比正常模式下的负载阻抗更低的阻抗。
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公开(公告)号：KR100287280B1
公开(公告)日：2001-04-16
申请号：KR1019970069739
申请日：1997-12-17
Applicant: 한국과학기술원
IPC: H03F3/26
Abstract: PURPOSE: A parallel push-pull amplifier using a complementary element is provided to obtain a large gain from a radio frequency by being operated as a class A or a class AB in a source common structure or an emitter common structure. CONSTITUTION: An active element(41) is used for amplifying a half-wave of an input signal. An anti-active element(42) has a duality to the active element(41). The anti-active element(42) is used for amplifying the remaining half-wave. A plurality of bias circuits(43,44) are used for setting up an operating point of the active element(41) and the anti-active element(42). The active element(41) and the anti-active element(42) represent a corresponding relationship such as an NMOS and a PMOS of a MOSFET or an NPN type and a PNP type of a BJT.
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公开(公告)号：KR1020010002996A
公开(公告)日：2001-01-15
申请号：KR1019990023098
申请日：1999-06-19
Applicant: 한국과학기술원
IPC: G06F7/49
Abstract: PURPOSE: A FPGA(Field Programmable Gate Array) having a RTBR DPL(Run Time Block Reconfigurable Data Path Logic) is provided to have the excellent efficiency by optimally sharing with a CFB(Configurable Function Block) and the RTBR DPL. CONSTITUTION: A combination operator comprises a 4bit multiplier(41) and the first and the second adder/subtracter(42,43). The 4bit multiplier(41) sums partially input data. The first adder/subtracter(42) sums the rest ply. The second adder/subtracter(43) adds/subtracts. A RTBR DPL comprises the first multiplexer(45), two registers(44), second multiplexers(46) and many configuration memories. The first multiplexer(45) selects the multiplication or the addition/subtraction by connecting with the multiplier(41) and the second adder/subtracter(43). The registers(44) are programmable as a latch or a flipflop by connecting with the first multiplexer(45) and the first adder/subtracter(42). One second multiplexers(46) select an output of the register(44) and the first multiplexer(45). The other second multiplexer(46) selects an output of the register(44) and the first adder/subtracter(42). The configurable memories decide the operation and the selection.
Abstract translation: 目的：提供具有RTBR DPL（运行时间块可重配置数据路径逻辑）的FPGA（现场可编程门阵列），通过与CFB（可配置功能块）和RTBR DPL进行最佳共享，具有极好的效率。 构成：组合运算符包括4位乘法器（41）和第一和第二加法器/减法器（42,43）。 4位乘法器（41）将部分输入数据相加。 第一加法器/减法器（42）对其余的层进行求和。 第二加法器/减法器（43）加/减。 RTBR DPL包括第一多路复用器（45），两个寄存器（44），第二多路复用器（46）和许多配置存储器。 第一多路复用器（45）通过与乘法器（41）和第二加法器/减法器（43）连接来选择乘法或加法/减法。 通过与第一多路复用器（45）和第一加法器/减法器（42）连接，寄存器（44）可编程为锁存器或触发器。 一个第二复用器（46）选择寄存器（44）和第一多路复用器（45）的输出。 另一第二多路复用器（46）选择寄存器（44）和第一加法器/减法器（42）的输出。 可配置存储器决定操作和选择。
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公开(公告)号：KR1020000028192A
公开(公告)日：2000-05-25
申请号：KR1019980046333
申请日：1998-10-30
Applicant: 한국과학기술원
IPC: H04B1/16
CPC classification number: H04B1/0003 , H03B5/326 , H04B1/28 , Y10T29/42
Abstract: PURPOSE: A structure of an one-chip radio having a thin or a thick piezoelectric crystal on a monolithic IC(integrated circuit) and a preparation method thereof are provided to make easy the connection between an IC and a piezoelectric crystal device on a silicon substrate and to integrate the IC with a high performance manual circuit by using the general preparation method of a semiconductor device. CONSTITUTION: A preparation process of an one-chip radio is perform by depositing a metal layer(102) such as aluminum or gold on the area of a quartz wafer(104) on a substrate(101). And, epoxy resin(103) for bonding is coated for a thickness of 1-3micrometer in a spin coating method for bonding the quartz wafer thereon. Then, a mechanical polishing is applied for polishing the 600micrometer of quartz wafer to 100micrometer. Finally, a metal layer(105) of an acoustic surface wave resonator is formed on a piezoelectric layer by using optical lithography and etching for connecting the crystal resonator to an oscillator circuit on the silicon substrate by using a metal wire(106).
Abstract translation: 目的：提供一种在单片IC（集成电路）上具有薄或厚的压电晶体的单芯片无线电结构及其制备方法，以便容易地在硅衬底上的IC与压电晶体器件之间的连接 并且通过使用半导体器件的一般制备方法将IC与高性能手动电路集成。 构成：通过在基板（101）上的石英晶片（104）的区域上沉积诸如铝或金的金属层（102）来执行单片无线电的制备过程。 并且，在其上粘接石英晶片的旋转涂布方法中，用于粘合的环氧树脂（103）以1-3微米的厚度被涂覆。 然后，将600微米的石英晶片抛光至100微米，进行机械抛光。 最后，通过使用光刻法和蚀刻法，通过使用金属线（106）将晶体谐振器连接到硅衬底上的振荡电路，在压电层上形成声表面波谐振器的金属层（105）。
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公开(公告)号：KR100139506B1
公开(公告)日：1998-07-15
申请号：KR1019940025687
申请日：1994-10-07
CPC classification number: G01P15/0922 , G01P15/0802 , G01P15/09 , G01P15/123 , G01P15/125 , G01P21/00 , G01P2015/0828
Abstract: 본 발명은 자체진단 기능을 구비한 대칭질량형 가속도계 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 에어백, 능동현가, 항법시스템 등 자동차용 전장시스템이나 변위, 속도, 진동, 가속도 및 각 가속도 측정을 위한 가전, 산업용 전자계측시스템 구성에 사용할 목적으로 동일크기의 질량체를 보(beam)의 양면에 각각 배치하여 질량편심을 없앰으로써 횡방향 감도(cross-axis sensitivity)를 향상시킴과 동시에, 양쪽 질량체간의 상대위치를 조절함으로써 자체진단(self-diagnosis)용 구조물의 설치가 가능하게끔 고안한 대칭질량형 가속도계 및 그 제조방법에 관한 것이다.
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