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    Voltage buffering arrangement in dynamic CMOS memory, i.e. DRAM
    73.
    发明专利
    Voltage buffering arrangement in dynamic CMOS memory, i.e. DRAM 未知

    公开(公告)号：DE19946201C1

    公开(公告)日：2000-12-14

    申请号：DE19946201

    申请日：1999-09-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  ZIBERT MARTIN

    IPC: G11C8/08 ,  G11C11/4074 ,  H01L21/761 ,  H01L27/02 ,  H01L27/108 ,  H01L23/58

    Abstract: The arrangement includes a p-conductive semiconductor substrate (7), an n-conductive tub structure (5, 6) provided in the semiconductor substrate, a p-conductive semiconductor area (4) included by the tub structure, and an NMOS transistor (1) provided in the p-conductive semiconductor area. The n-conductive tub structure is supplied with a higher voltage than the p-conductive semiconductor area and the p-conductive semiconductor substrate. The semiconductor substrate is put at a low supply voltage (VSS) and the tub structure at a high supply voltage, so that a voltage to be buffered is applied at the tub structure. The voltage to be buffered may be a negative word conductor blocking voltage or an amplified word conductor voltage.

    Integrated circuit arrangement with transistors working voltage control e.g. for differential amplifier
    74.
    发明专利
    Integrated circuit arrangement with transistors working voltage control e.g. for differential amplifier 未知

    公开(公告)号：DE19950543C1

    公开(公告)日：2000-11-23

    申请号：DE19950543

    申请日：1999-10-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  KAISER ROBERT

    IPC: H03K19/00 ,  H01L23/58 ,  G05F1/10

    Abstract: An integrated circuit includes a first control unit (C1) for controlling the operating/working voltage of first conductivity type transistors (T1,T2), the latter having substrate terminals for supply of substrate potentials (Vnw;Vpw). The control unit has an input for a desired value (VTnsoll) and an input for an actual value (VTnist) of the working voltage of the transistors of the first conductivity type (T1,T2) as well as an output connected to the substrate terminals of the first conductivity type transistors. A second control unit (C2) controls the working voltage of the second conductivity type transistors (T3,T4) and has inputs for a desired value and an actual value (VTpist) of the working voltage of these transistors (T3,T4), and an output connected to the substrate terminals of these transistors (T3,T4). A desired value for the working voltage of the transistors (T3,T4) is supplied to the desired value input of the second control unit (C2), and is proportional to the amount of the actual value (VTnist) of the working voltage of the first conductivity type transistors (T1,T2).

    77.
    发明专利
    未知

    公开(公告)号：DE10117614B4

    公开(公告)日：2005-06-23

    申请号：DE10117614

    申请日：2001-04-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

    IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    Abstract: A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.

    78.
    发明专利
    未知

    公开(公告)号：DE10102000B4

    公开(公告)日：2004-04-08

    申请号：DE10102000

    申请日：2001-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

    IPC: H01L23/50 ,  H01L23/544 ,  H01L23/58

    Abstract: A description is given of an integrated circuit having components and a method for checking a connection configuration of bonding pads. The integrated circuit has an identification circuit that identifies a connection of the bonding pads to external circuits. After the identification of the connected bonding pads, the data width of the input/output circuit is preferably programmed accordingly. In this way, self-detection and automatic programming are possible without data inputting from the outside.

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