公开(公告)号：DE102009044391A1

公开(公告)日：2010-05-20

申请号：DE102009044391

申请日：2009-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POSTNIKOV SERGEI ,  SCHULZ THOMAS

IPC: H01L21/027 ,  G03F7/20

Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

公开(公告)号：DE102008038170A1

公开(公告)日：2009-05-14

申请号：DE102008038170

申请日：2008-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAPELMANN CHRIS ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/786

Abstract: A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.

公开(公告)号：DE50310119D1

公开(公告)日：2008-08-21

申请号：DE50310119

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: H01L27/115 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：DE112006000241T5

公开(公告)日：2008-04-10

申请号：DE112006000241

申请日：2006-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/423

Abstract: A semiconductor device includes a source region, a drain region, and a fin that connects the source region to the drain region. A gate electrode having a substantially planar surface overlies the fin and is positioned between the drain region and the source region. A first set of spacers is positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region. A second set of spacers is positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers. At least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode.

公开(公告)号：DE50011071D1

公开(公告)日：2005-10-06

申请号：DE50011071

申请日：2000-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L29/786

公开(公告)号：DE10351201B3

公开(公告)日：2005-07-14

申请号：DE10351201

申请日：2003-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  SCHULZ THOMAS ,  EVERSMANN BJOERN

IPC: H01L21/84 ,  H01L27/12 ,  B81C1/00 ,  B81B7/02 ,  C12Q1/02 ,  G01N27/12 ,  G01N33/483 ,  H01L27/092

Abstract: Producing a semiconductor neuro-sensor, comprising a semiconductor microstructure (10) that incorporates numerous transistors (12), where the semiconductor foundation structure (10) is disc-shaped and has an essentially flat disc surface (20), is new. Producing a semiconductor neuro-sensor, comprises a semiconductor microstructure (10) that incorporates numerous transistors (12), where the semiconductor foundation structure (10) is disc-shaped and has an essentially flat disc surface (20). In a second stage a micro-structured sensor structure (30, 30') is formed with numerous semiconductor sensor elements, each in contact with a sensor dielectric agent (40). The sensor structure (30, 30') is disc shaped and has an essentially flat disc surface (44) facing the sensor element surface. The sensor structure is then formed by etching the dielectric agent (40), followed by hardening at above 400 [deg]C. The sensor structure (30, 30') is then wafer-bonded to the semiconductor foundation structure (10), followed by positioning of the electrical contacts (62) between the sensor elements and the transistors (12). An independent claim is also included for a commensurate sensor assembly.

公开(公告)号：DE10241172A1

公开(公告)日：2004-03-18

申请号：DE10241172

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  LYKEN R JOHANNES

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

公开(公告)号：DE10241171A1

公开(公告)日：2004-03-18

申请号：DE10241171

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  HOFMANN FRANZ ,  SPECHT MICHAEL

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of fins made of semiconductor material which are spaced apart from one another, a multiplicity of channel regions and contact regions being formed in each of the fins, a multiplicity of word lines, a multiplicity of storage layers, at least one of the storage layers being arranged between each of the channel regions and the word line, and a multiplicity of bit lines, the longitudinal axes of first bit line portions running parallel to a first bit line direction and the longitudinal axes of second bit line portions running parallel to a second bit line direction, the second bit line direction being rotated relative to the first bit line direction, each of the bit lines being electrically connected to a multiplicity of the contact regions, wherein, between two contact regions of the same fin that are connected to one of the bit lines, a contact region is not connected to the respective bit line.

公开(公告)号：DE10211337A1

公开(公告)日：2003-10-09

申请号：DE10211337

申请日：2002-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PACHA CHRISTIAN ,  SCHULZ THOMAS

IPC: G11C11/419 ,  G11C14/00 ,  G11C11/41

Abstract: A circuit-arrangement has a SRAM-memory cell, a temporary memory circuit, first and second non-volatile memory cells (105,106) coupled to first and second memory nodes (102,103) respectively such that, in a first operational state, a first electrical potential is available at one of the nodes and a second potential is available at the other node and, in a second operational state, the first memory node is placed at the electrical potential at which it was placed in the first operational state and the second memory node is placed at the electrical potential at which it was placed in the first operational state, by utilizing the physical state of the first and of the second non-volatile memory cells (105,106), respectively. An Independent claim is given for a method of running a circuit-arrangement

公开(公告)号：DE10137217A1

公开(公告)日：2003-02-27

申请号：DE10137217

申请日：2001-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.