公开(公告)号：DE60311125D1

公开(公告)日：2007-02-22

申请号：DE60311125

申请日：2003-07-11

Applicant: INTEL CORP

Inventor： MA QING ,  SHIM DONG

IPC: B81B3/00 ,  H03H9/05 ,  H03H9/02 ,  H03H9/25

Abstract: Microelectromechanical system (MEMS) apparatus and methods for surface acoustic wave (SAW) switching are disclosed. The apparatus includes a piezoelectric substrate having spaced apart input and output SAW transducers. A MEMS switch is arranged between the input and output SAW transducers The MEMS switch has a deformable member in electromagnetic communication with one or more actuation electrodes formed on or above the substrate. The deformable member is deformable to mechanically contact the substrate to deflect or absorb a SAW generated by the input SAW transducer.

公开(公告)号：MY122887A

公开(公告)日：2006-05-31

申请号：MYPI20022146

申请日：2002-06-10

Applicant: INTEL CORP

Inventor： MA QING ,  CHENG PENG ,  RAO VALLURI

IPC: H01F5/00 ,  H01F17/00 ,  H01F21/12 ,  H01H59/00

Abstract: A TUNABLE INDUCTOR IS DISCLOSED. THE TUNABLE INDUCTOR COMPRISES A HELICAL (70) OR SPIRAL (92) INDUCTOR FORMED ON A SEMICONDUCTOR SUBSTRATE (146) HAVING AN INPUT AND AN OUTPUT. THE HELICAL INDUCTOR (70) HAS A FULL LENGTH THAT PROVIDES A FULL INDUCTANCE. ALSO, A FULL INDUCTANCE SWITCH IS DISPOSED BETWEEN THE OUTPUT AND THE FULL LENGTH OF THE HELICAL INDUCTOR. FINALLY, AT LEAST ONE MICROELECTROMECHANICAL (MEMS) SWITCH (146) IS DISPOSED BETWEEN THE OUTPUT AND AN INTERMEDIATE LOCATION OF THE HELICAL INDUCTOR. FIG. 28

公开(公告)号：GB2392329B

公开(公告)日：2005-03-16

申请号：GB0318456

申请日：2003-08-06

Applicant: INTEL CORP

Inventor： WANG LI-PENG ,  BAR-SADEH EYAL ,  RAO VALLURI ,  HECK JOHN ,  MA QING ,  TRAN QUAN ,  TALALYEVSKY ALEXANDER ,  GINSBURG EYAL

IPC: H03H9/24 ,  H03H3/02 ,  H03H9/56 ,  H03H9/17 ,  H03H9/58

Abstract: A film bulk acoustic resonator filter (10) may be formed with a plurality of interconnected series and shunt film bulk acoustic resonators (38) formed on the same membrane (35). Each of the film bulk acoustic resonators (38) may be formed from a common lower conductive layer which is defined to form the bottom electrode (32) of each film bulk acoustic resonator (38). A common top conductive layer may be defined to form each top electrode (36) of each film bulk acoustic resonator (38). A common piezoelectric film layer (34), that may or may not be patterned, forms a continuous or discontinuous film.

公开(公告)号：AU2003300809A1

公开(公告)日：2004-07-29

申请号：AU2003300809

申请日：2003-12-03

Applicant: INTEL CORP

Inventor： TRAN QUAN ,  MA QING ,  HAYDEN JOSEPH III ,  CHOU TSUNG-KUAN ALLEN

IPC: H01P3/00 ,  H01P11/00 ,  H05K1/02 ,  H05K3/24

Abstract: Coplanar waveguides have a center signal line and a pair of ground lines on either side formed of a sputtered material such as gold (Au). Such waveguides are subject to what is known as the edge effect at high frequency operation causing currents to concentrate and flow along adjacent edges of the lines. Providing a thicker plated layer only on adjacent edges of the lines provide substantial performance improvements over sputtered lines alone while saving significant amount of Au, thus reducing costs.

公开(公告)号：GB2392329A

公开(公告)日：2004-02-25

申请号：GB0318456

申请日：2003-08-06

Applicant: INTEL CORP

Inventor： WANG LI-PENG ,  BAR-SADEH EYAL ,  RAO VALLURI ,  HECK JOHN ,  MA QING ,  TRAN QUAN ,  TALALYEVSKY ALEXANDER ,  GINSBURG EYAL

IPC: H03H9/24 ,  H03H3/02 ,  H03H9/56 ,  H03H9/17 ,  H03H9/58

Abstract: An FBAR filter 10 may be formed with a plurality of interconnected series and shunt film bulk acoustic resonators 38 formed on the same membrane 35. Each of the film bulk acoustic resonators 38 may be formed from a common lower conductive layer which is defined to form the bottom electrode 32 of each film bulk acoustic resonator 38. A common top conductive layer may be defined to form each top electrode 36 of each film bulk acoustic resonator 38. A common piezoelectric film layer 34 that may or may not be patterned, forms a continuous or discontinuous film. The plurality of FBARs 38 may be formed over a single backside cavity.

公开(公告)号：AU2003243482A1

公开(公告)日：2004-01-06

申请号：AU2003243482

申请日：2003-06-10

Applicant: INTEL CORP

Inventor： MA QING ,  CHOU TSUNG-KUAN

IPC: B81C1/00 ,  B81B7/00 ,  B81B7/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/66 ,  H01L27/04

Abstract: A conductive bridge (16) in a second conductive layer may be utilized to join a pair of spaced apart conductive strips (12) in a first conductive layer. A gap (44) between the first and second strips (12) may be bridged by the bridge (16) while isolating both the first and second strips (12) and the bridge (16) itself from another conductor (18) which extends through the gap (44) between the first and second strips (12).

公开(公告)号：AU9633201A

公开(公告)日：2002-04-08

申请号：AU9633201

申请日：2001-09-25

Applicant: INTEL CORP

Inventor： MA QING ,  MAVEETY JAMES ,  TRAN QUAN

IPC: H01L23/36 ,  H01L23/367

Abstract: A microelectronic die is aligned with a package substrate and attached to it using solder balls. A specially shaped heat spreader, preferably with a coefficient of thermal expansion (CTE) similar to that of silicon, is attached to the back side of the die using a heat-conducting adhesive. An epoxy-based material is flowed into the gap between the die, the substrate, and the heat spreader via a through-hole in either the substrate or the heat spreader using a dispense process or a transfer molding process. By positioning the heat spreader to abut the die corners and/or edges, the stresses on the die are substantially reduced or eliminated.

公开(公告)号：AU8715001A

公开(公告)日：2002-03-26

申请号：AU8715001

申请日：2001-09-07

Applicant: INTEL CORP

Inventor： MA QING

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A packaging technology that fabricates a microelectronic package including build-up layers, having conductive traces, on an encapsulated microelectronic die and on other packaging material that surrounds the microelectronic die, wherein an moisture barrier structure is simultaneously formed with the conductive traces. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side. Packaging material(s) is disposed adjacent the microelectronic die side(s), wherein the packaging material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then formed on the first dielectric material layer to electrically contact the microelectronic die active surface. A barrier structure proximate an edge of the microelectronic package is formed simultaneously out of the same material as the conductive traces.

公开(公告)号：DE112010004890B4

公开(公告)日：2016-12-01

申请号：DE112010004890

申请日：2010-11-11

Applicant: INTEL CORP

Inventor： MA QING ,  RAO VALLURI R ,  TRAN QUAN A ,  SANKMAN ROBERT L ,  SWAN JOHANNA M

IPC: H01L21/84 ,  H01L21/60 ,  H01L23/485 ,  H01L23/50

Abstract: Verfahren (300), das Folgendes umfasst: Bereitstellen eines Glaskörpers, der eine Reihe von eingebetteten leitfähigen Drähten aufweist (330); und Schneiden von Scheiben aus dem Glaskörper (335), wobei jede Scheibe eine erste Fläche (412) und eine gegenüberliegende zweite Fläche (414) aufweist, die im Wesentlichen parallel zu der ersten Fläche ist, wobei ein Teil jedes eingebetteten Drahts in jeder der Scheiben bleibt und sich von der ersten Fläche (412) zu der zweiten Fläche (414) der Scheibe erstreckt, wobei jeder eingebettete Drahtteil einen einer entsprechenden Reihe von Leitern bereitstellt; wobei zwei oder mehrere Scheiben einen Glaskern für ein Substrat bereitstellen (345); wobei der Glaskörper Ausrichtungselemente enthält (355), und wobei das Verfahren weiterhin das Ausrichten der zwei oder mehr Scheiben unter Verwendung der Ausrichtungselemente umfasst (345), während die zwei oder mehr Scheiben miteinander verbunden werden, um den Glaskern bereitzustellen.

公开(公告)号：DE112013003246T5

公开(公告)日：2015-04-02

申请号：DE112013003246

申请日：2013-06-05

Applicant: INTEL CORP

Inventor： EID FERAS ,  MA QING ,  TEH WENG HONG ,  LIN KEVIN L

IPC: H01L23/62 ,  H01L25/07

Abstract: Ein Halbleitergehäuse, das eine darin befindliche mechanische Sicherung besitzt und Verfahren zum Formen eines Halbleitergehäuses mit einer darin befindlichen mechanischen Sicherung werden beschrieben. Beispielsweise umfasst eine Halbleiterstruktur ein Halbleitergehäuse. Ein Halbleiter-Die ist im Halbleitergehäuse untergebracht. Ein Baustein mit einem mikro-elektromechanischen System (MEMS) ist im Halbleitergehäuse untergebracht. Der MEMS-Baustein weist einen schwebenden Teil auf. Eine mechanische Sicherung ist im Halbleitergehäuse untergebracht und entweder gekoppelt mit oder entkoppelt vom schwebenden Teil des MEMS-Bausteins.