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    CELLULE DE MEMOIRE VOLATILE PREENREGISTREE
    78.
    发明专利
    CELLULE DE MEMOIRE VOLATILE PREENREGISTREE 未知

    公开(公告)号：FR2877143A1

    公开(公告)日：2006-04-28

    申请号：FR0411360

    申请日：2004-10-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  LASSEUGUETTE JEAN ,  FOURNEL RICHARD

    IPC: H01L27/11 ,  G11C14/00

    Abstract: L'invention a pour objet de proposer une cellule de mémoire de type SRAM capable de mémoriser de manière non volatile une donnée. Une cellule de mémoire comporte deux inverseurs 20 et 21 montés tête-bêche pour mémoriser un bit. Chaque inverseur 20 ou 21 comporte un transistor 24 ou 26 d'un premier type et un transistor 25 ou 27 d'un second type. La concentration de porteurs dans le canal de conduction du transistor 24 du premier type de l'un des inverseurs 20 est différente de la concentration de porteurs dans le canal de conduction du transistor 26 du premier type de l'autre des inverseurs 21 de sorte que les inverseurs aient des tensions de seuil différentes.

    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers
    79.
    发明专利
    Memory cell of type permanent static random-access memory (SRAM), comprises two interconnected inverter circuits and transistors for programming by degradation of gate oxide layers 未知

    公开(公告)号：FR2849260A1

    公开(公告)日：2004-06-25

    申请号：FR0216558

    申请日：2002-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

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