公开(公告)号：US10015880B1

公开(公告)日：2018-07-03

申请号：US14565227

申请日：2014-12-09

Applicant: Multek Technologies Ltd.

Inventor： Mark Bergman ,  Joan K. Vrtis

IPC: H05K1/02 ,  H05K3/22

CPC classification number: H05K1/0271 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/0386 ,  H05K1/0393 ,  H05K1/144 ,  H05K1/148 ,  H05K3/22 ,  H05K3/4691 ,  H05K2201/0137 ,  H05K2201/05 ,  H05K2201/058 ,  H05K2201/09945 ,  H05K2201/0999 ,  H05K2201/2009

Abstract: A rip stop material is attached at a stress area of a flexible circuit board in order to strengthen the flexible circuit board and minimize ripping and cracking in the polyimide and/or the copper conductors of the circuit. A rip stop transition layer is formed and deposited at a location on the flexible circuit in order to minimize, reduce, if not preventing cracking and ripping of the circuit as it is bent and flexed. The rip stop transition layer can be placed at different locations on and within the flexible circuit in order to minimize cracking and ripping as the flexible circuit is bent, flexed and twisted.

公开(公告)号：US20180139842A1

公开(公告)日：2018-05-17

申请号：US15870865

申请日：2018-01-13

Applicant: Avary Holding (Shenzhen) Co., Limited. ,  HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd.

Inventor： FANG-BO XU ,  PENG WU ,  JIAN-QUAN SHEN ,  KE-JIAN WU

IPC: H05K1/09 ,  H05K1/02 ,  H05K3/28 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/09 ,  H05K1/0225 ,  H05K1/111 ,  H05K3/0026 ,  H05K3/188 ,  H05K3/282 ,  H05K3/4682 ,  H05K2201/0137 ,  H05K2201/0154 ,  H05K2203/0228 ,  H05K2203/107 ,  Y10T29/49155

Abstract: A printed circuit board with high-capacity and high-current copper circuit includes a conductive trace, a first protecting layer, and a second protecting layer on opposite sides of the conductive trace. The conductive trace includes a basic conductive trace pattern, a first conductive trace pattern, and a second conductive trace pattern. The first and second conductive trace patterns are directly formed on opposite surfaces of the basic copper conductive trace pattern. A width of trace of the first conductive trace pattern is the same as a line width of the second conductive trace pattern.

公开(公告)号：US20180027668A1

公开(公告)日：2018-01-25

申请号：US15541687

申请日：2015-12-17

Applicant: FUJIKURA LTD.

Inventor： Masahiro Kaizu ,  Masateru Ichikawa

IPC: H05K3/46 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K3/4644 ,  H01B1/22 ,  H05K1/115 ,  H05K3/10 ,  H05K3/12 ,  H05K2201/0137 ,  H05K2201/0929 ,  H05K2201/09609 ,  H05K2203/0195 ,  H05K2203/0776 ,  H05K2203/1131

Abstract: A method of manufacturing a conductive layer on a support body includes a first process of forming a precursor layer containing at least one of metal particles and metal oxide particles on the support body; a second process of forming a sintering layer by irradiating an electromagnetic wave pulse on the precursor layer; and a third process of compressing the sintering layer. The conductive layer is formed by repeating the first to third processes “N” times, where “N” denotes a natural number equal to or greater than 2, on the same location of the support body, and the third process performed in the first to (N−1)th operations includes forming a surface of the sintering layer in an uneven shape.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09730329B2

公开(公告)日：2017-08-08

申请号：US14360906

申请日：2011-11-29

Applicant: Zhongyao Yu ,  Xia Zhang

Inventor： Zhongyao Yu ,  Xia Zhang

IPC: H01L29/06 ,  H05K1/18 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L25/16 ,  H01L25/00 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/188 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24135 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/12042 ,  H05K1/115 ,  H05K1/185 ,  H05K3/46 ,  H05K3/4652 ,  H05K2201/0137 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09509 ,  H01L2924/00

Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.

公开(公告)号：US09521748B1

公开(公告)日：2016-12-13

申请号：US14565267

申请日：2014-12-09

Applicant: Multek Technologies Ltd.

Inventor： Mark Bergman ,  Joan K. Vrtis

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/22

CPC classification number: H05K1/0271 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/0386 ,  H05K1/0393 ,  H05K1/144 ,  H05K1/148 ,  H05K3/22 ,  H05K3/4691 ,  H05K2201/0137 ,  H05K2201/05 ,  H05K2201/058 ,  H05K2201/09945 ,  H05K2201/0999 ,  H05K2201/2009

Abstract: Mechanical measures strengthen a flexible circuit board or deformable electronic by manipulating the location and/or intensity of the stress concentration or to limit bending, torsion, and stretching. A material layer is patterned onto the flexible circuit board with a specific pattern and place of deposition in order to modify the stress concentration and profile of the circuit board and increase its overall strength. The material layer may be configured to modify the stress concentrations during bending away from the weak points in the assembly or to spread the stress during bending by increasing the radius of the bend curvature and therefore decreasing the chance of mechanical failure.

Abstract translation: 机械措施通过操纵应力集中的位置和/或强度或限制弯曲，扭转和拉伸来加强柔性电路板或可变形电子。 将材料层图案化到具有特定图案和沉积位置的柔性电路板上，以便改变电路板的应力集中和轮廓并增加其整体强度。 材料层可以被配置为在远离组件中的弱点的过程中修改弯曲期间的应力集中，或者通过增加弯曲曲率半径来扩展弯曲过程中的应力，从而降低机械故障的机会。

公开(公告)号：US20150257260A1

公开(公告)日：2015-09-10

申请号：US14198658

申请日：2014-03-06

Applicant: Carolyn Rae Ellinger

Inventor： Carolyn Rae Ellinger

IPC: H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0284 ,  C23C16/345 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2924/0002 ,  H05K1/09 ,  H05K2201/0137 ,  H05K2201/0326 ,  H05K2201/09045 ,  H01L2924/00

Abstract: A vertically separated electrode structure includes a polymeric material post on a substrate. An inorganic material cap covers the top of the post and extends beyond an edge of the post in at least a width dimension to define a first reentrant profile. A first electrode is located over the cap. A second electrode is located over the substrate and not over the post. The second electrode is adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. The first electrode and second electrode have the same material composition and layer thickness.

Abstract translation: 垂直分离的电极结构包括在基底上的聚合物材料柱。 无机材料盖覆盖柱的顶部并且在至少一个宽度尺寸上延伸超出柱的边缘以限定第一凹槽轮廓。 第一电极位于盖上。 第二电极位于衬底上并且不在柱上。 第二电极在折返轮廓中与柱的边缘相邻，使得当与衬底表面正交测量时，第一电极和第二电极之间的距离大于零。 第一电极和第二电极具有相同的材料组成和层厚度。

公开(公告)号：US09107308B2

公开(公告)日：2015-08-11

申请号：US14380981

申请日：2013-02-26

Applicant: Nan Jiang ,  Zvi Yaniv

Inventor： Nan Jiang ,  Zvi Yaniv

IPC: H05K1/03 ,  H05K1/05 ,  C04B41/90 ,  C04B41/00 ,  C04B41/52 ,  H05K1/02 ,  H05K1/09 ,  H05K3/12 ,  H01L23/373 ,  H05K1/18 ,  C04B111/00

CPC classification number: H05K1/053 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00844 ,  H01L23/373 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/181 ,  H05K3/12 ,  H05K2201/0104 ,  H05K2201/0137 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/06 ,  H05K2201/10106 ,  H01L2924/00 ,  C04B35/522 ,  C04B41/4539 ,  C04B41/5001 ,  C04B41/5031 ,  C04B41/5089 ,  C04B41/5059 ,  C04B41/5092 ,  C04B41/522 ,  C04B41/5063 ,  C04B41/5064 ,  C04B41/4535 ,  C04B41/4572 ,  C04B41/5127

Abstract: Different kinds of printing pastes or inks are utilized in various combinations to develop multiple ceramic dielectric layers on graphitic substrates in order to create effective dielectric ceramic layers that combine good adhesion to both graphitic substrates and printed copper traces, and strong insulating capability. The pastes or inks may comprise a high thermal conductivity powder.

Abstract translation: 不同种类的印刷浆料或油墨被用于各种组合以在石墨基材上形成多个陶瓷电介质层，以便产生有效的介电陶瓷层，其与石墨基材和印刷的铜迹线具有良好的粘合性，并具有很强的绝缘性能。 糊剂或油墨可以包含高导热性粉末。

公开(公告)号：US20150022984A1

公开(公告)日：2015-01-22

申请号：US14495513

申请日：2014-09-24

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Hyungmi JUNG ,  Jaechoon Cho ,  Choonkeun Lee ,  Taesung Jeong ,  Seungeun Lee ,  Jinsun Park ,  Yeena Shin

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/00 ,  H05K1/03 ,  H05K3/30

CPC classification number: H05K1/183 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K1/0353 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0023 ,  H05K3/30 ,  H05K3/4676 ,  H05K2201/0137 ,  H05K2201/0209 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

Abstract: An embedded printed circuit board and a method of manufacturing the same. The embedded printed circuit board includes: an insulating layer on which a cavity is formed; a chip mounted on the cavity; and a circuit layer formed on the insulating layer, wherein the insulating layer is made of photosensitive compositions including photosensitive monomer and photoinitiator. As a result, the cavity can be formed by selectively using only the insulating layer, thereby making it possible to secure a degree of freedom in the design of the embedded printed circuit board.

Abstract translation: 一种嵌入式印刷电路板及其制造方法。 嵌入式印刷电路板包括：形成空腔的绝缘层; 安装在腔体上的芯片; 以及形成在所述绝缘层上的电路层，其中所述绝缘层由包括光敏单体和光引发剂的感光组合物制成。 结果，可以通过仅选择性地使用绝缘层来形成空腔，从而可以确保嵌入式印刷电路板的设计的自由度。

公开(公告)号：US20150021071A1

公开(公告)日：2015-01-22

申请号：US14383972

申请日：2013-02-28

Applicant: ISHIHARA CHEMICAL CO. LTD.

Inventor： Yuichi Kawato ,  Tomohiro Mita ,  Yusuke Maeda ,  Tomio Kudo

IPC: H05K3/38 ,  H05K1/02 ,  H05K3/24 ,  H05K1/03

CPC classification number: H05K3/38 ,  H05K1/0296 ,  H05K1/0313 ,  H05K1/097 ,  H05K3/245 ,  H05K3/246 ,  H05K3/386 ,  H05K2201/0129 ,  H05K2201/0137 ,  H05K2201/0154 ,  H05K2201/032 ,  H05K2203/1126 ,  H05K2203/1131 ,  Y10T29/49163

Abstract: In a conductive film formed by photo sintering of a film composed of copper particulates, adhesiveness to a base material of the conductive film is improved. A circuit board includes a circuit including a conductive film, and a substrate. The circuit board further includes a resin layer between the substrate and the conductive film. The substrate is made of a non-thermoplastic base material. The resin layer contains a thermoplastic resin. The conductive film is formed by photo sintering of a film composed of copper particulates, and thus improving adhesiveness of the conductive film to the base material through the resin layer.

Abstract translation: 在由铜微粒构成的薄膜进行光烧结而形成的导电膜中，与导电膜的基材的粘附性提高。 电路板包括具有导电膜和基板的电路。 电路板还包括在基板和导电膜之间的树脂层。 基材由非热塑性基材制成。 树脂层含有热塑性树脂。 导电膜由铜微粒构成的薄膜进行光烧结而形成，从而提高导电膜与基材通过树脂层的密合性。