A connector and a mounting method therefor
    75.
    发明公开
    A connector and a mounting method therefor 有权
    Verbinder和Motageverfahren

    公开(公告)号:EP1758208A1

    公开(公告)日:2007-02-28

    申请号:EP06017087.5

    申请日:2006-08-16

    Inventor: Nakano, Hiroshi

    Abstract: An object of the present invention is to enable a reduction in bonding strength to a circuit board to be restrained while letting bubbles created in solder escape.
    A circuit board connector 1 according to the present invention is provided with a connector housing 10, male terminals 20 and fixing members 30. Each fixing member 30 is formed by bending a metal flat plate into an L-shape, and comprised of a mounting portion 31 used to mount the fixing member 30 into the connector housing 10, and a bonding portion 32 to be soldered. The bonding portion 32 is formed with connecting pieces 33 by making substantially "gate"-shaped cuts in the bonding portion 32 to penetrate the bonding portion 32 and then bending parts enclosed by these cuts upward. A clearance S is defined between the bottom edge of the leading end of each connecting piece 33 and the hole wall of a corresponding through hole 34 facing this bottom edge. The clearances S communicate with the through holes 34 formed upon bending the connecting pieces 33. The lower surfaces of the connecting pieces 33 and the inner surfaces of the through holes 34 can be soldered.

    Abstract translation: 本发明的一个目的是在焊接产生的气泡逸出的同时,能够抑制与电路板的接合强度的降低。 根据本发明的电路板连接器1设置有连接器壳体10,阳端子20和固定构件30.每个固定构件30通过将金属平板弯曲成L形而形成,并且包括安装部分 31用于将固定构件30安装到连接器壳体10中,以及接合部32被焊接。 接合部32通过在接合部32中形成大致“门”状切口而形成有连接片33,以穿透接合部32,然后将由这些切口包围的部分向上弯曲。 在每个连接件33的前端的底部边缘与面向该底部边缘的对应的通孔34的孔壁之间限定间隙S. 间隙S与弯曲连接片33时形成的通孔34连通。连接件33的下表面和通孔34的内表面可被焊接。

    Lead pin for package boards
    79.
    发明申请
    Lead pin for package boards 失效
    封装板引脚

    公开(公告)号:US20100000761A1

    公开(公告)日:2010-01-07

    申请号:US12232316

    申请日:2008-09-15

    Abstract: Provided is a lead pin for package boards including a disk-shaped head of which the diameter increases toward the middle portion thereof and that has a hexagonal vertical cross-sectional shape; and a connection pin that is formed so as to project from the center of the upper surface of the head.

    Abstract translation: 提供一种用于封装板的引脚,包括直径朝向其中间部分增加的圆盘形头部,并且具有六边形垂直横截面形状; 以及形成为从头部的上表面的中心突出的连接销。

    METHOD AND APPARATUS TO REDUCE PIN VOIDS
    80.
    发明申请
    METHOD AND APPARATUS TO REDUCE PIN VOIDS 审中-公开
    减少PIN VOIDS的方法和装置

    公开(公告)号:US20090250824A1

    公开(公告)日:2009-10-08

    申请号:US12098311

    申请日:2008-04-04

    Abstract: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.

    Abstract translation: 半导体封装包括利用一个或多个引脚形成外部互连的基板。 引脚通过焊料与基板上的焊盘接合。 销可以各自具有可以具有接合表面的销头,其中接合表面可以包括中心部分和相对于中心部分逐渐变细的侧部部分。 在一些实施例中,接合表面可以包括圆形。 在一些实施例中,可以通过接合表面的形状提供气体逸出路径,以增加引脚拉伸强度和/或焊接强度。 该封装还可以包括表面光洁度,其可以包括具有减小厚度的钯层,以减少基于钯的IMC沉淀到焊料中的量。

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