Abstract:
PURPOSE: A method for manufacturing an oxide thin film transistor using a dry etching process is provided to prevent the degradation of and an IGZO oxide semiconductor thin film by forming a protecting layer. CONSTITUTION: In a method for manufacturing an oxide thin film transistor using a dry etching process is comprised of the steps: forming a first thin conductive film(203) functioned as a source and a drain electrode at an upper part of a substrate(201); forming an IGZO oxide semiconductor thin film(205) on the first thin conductive films; performing the IGZO oxide semiconductor thin film through a dry etching firstly; performing the IGZO oxide semiconductor thin film through dry etching secondly; forming an insulator film functioned as the gate insulating layer(207) on the IGZO oxide semiconductor thin film; and forming a second thin conductive film(209) functioned as the gate electrode on oxide insulator thin film.
Abstract:
A manufacturing method of a ZnO TFT is provided to reduce a defect inside a semiconductor thin film by controlling a deposition temperature after selecting oxygen plasma or ozone as oxygen precursor. A ZnO semiconductor film(30) is formed on a substrate(10) through an atomic layer deposition method using Zn precursor and ozone at a temperature of 250~350°C or Zn precursor and oxygen plasma at a temperature of 150~250°C. An insulation film(40) is formed on a top part of the ZnO semiconductor film through the atomic layer deposition method using the oxygen precursor selected from ozone or water at a temperature less than 250°C. A gate electrode(50) is formed on a top part of the insulation film. The ZnO semiconductor film has thickness of 5~40nm. The substrate is a substrate in which a source/drain electrode(20) is formed and a substrate in which the gate electrode and the insulation film are formed.
Abstract:
An electronic device using a phase change material, a phase change memory device, and a manufacturing method thereof are provided to make a programmable volume small by generating a phase change layer using a solid state reaction method. An insulation layer covers a first reaction layer in order to form a contact hole which exposes a part of a top part of the first reaction layer(208). A second reaction layer(210) is filled in the contact hole. A phase change layer(215) is formed between the first reaction layer and the second reaction layer. The phase change layer is formed by a solid state reaction of material used in the first reaction layer and material used in the second reaction layer. The phase change layer is made of material which is changed into an amorphous state and a crystalline state according to a current amount.
Abstract:
본 발명에 따른 상변화 메모리는 반도체 기판 위의 게이트 전극 및 상기 게이트 전극 양 옆으로 상기 반도체 기판에 형성된 제1 및 제2 불순물 영역을 포함하는 트랜지스터; 상기 제1 불순물 영역과 전기적으로 연결되는 비트라인; 및 상기 제2 불순물 영역과 전기적으로 연결되는 상변화 저항소자를 포함하되, 상기 상변화 저항소자는 도핑된 SiGe 층으로 형성된 하부 전극; 상기 하부 전극과 접촉하는 상변화층; 및 상기 상변화층과 연결된 상부 전극을 포함한다. 하부 전극으로 비저항이 높고, 열전도도가 낮은 도핑된 SiGe 를 채용함으로써 리셋 전류를 줄일 수 있고, 상변화 메모리 전체의 전력 소모를 줄일 수 있다. 상변화 메모리, 리셋 전류, 하부 전극, SiGe
Abstract:
An organic gate insulating layer and an organic thin film transistor are provided to minimize influence on other film by the organic gate insulating layer by forming the organic gate insulating layer with low permittivity, high chemical and thermal stability, and low absorption rate at a low temperature. A source electrode, a drain electrode and a gate electrode(20) are positioned on a surface of a substrate(10). An organic gate insulating layer(30) is interposed between the source electrode and the gate electrode and between the drain electrode and the gate electrode. The organic gate insulating layer includes polysiloxane or polysiloxane derivative. An organic active film contacts the organic gate insulating layer. The source electrode and the drain electrode are connected by the organic active film.
Abstract:
A phase change memory device which has a small contact between a phase change layer and a heating electrode, and a manufacturing method thereof are provided to decrease contact size and reset current by forming the heating electrode which has an upper end shorter than a lower end. The plural lower part electrodes(102a,102b) are formed on a semiconductor substrate(100). The plural heating electrodes(112a,112b) which have lower ends of shorter length than upper ends are formed on the lower electrodes. The plural phase change layers(114a,114b) are formed adjacent to the upper end of the heating electrode. The plural upper part electrodes(124a,124b) are formed on the phase change layers.
Abstract:
A PRAM(Phase change RAM) device and a method for manufacturing the same are provided to enhance reliability by using a heat-radiating layer having an optimum heat-radiating characteristic. A PRAM device comprises a lower electrode(110) formed on a semiconductor substrate, an upper electrode(150) formed on the lower electrode, and a PRAM layer formed between the lower electrode and the upper electrode. A heat-radiating layer(120) is formed between the upper electrode or the lower electrode and the PRAM. The heat-radiating layer includes a first heat-radiating layer(121) and a second heat-radiating layer(122). The first heat-radiating layer comes in contact with the PRAM layer. The second heat-radiating layer comes in contact with the first heat-radiating layer and is positioned between the first heat-radiating layer and the upper electrode or the lower electrode.
Abstract:
A method of fabricating a phase change memory device for obtaining high integration without a gap fill process is provided to reduce a manufacturing cost by reducing the number of processes without increasing the gap-fill process. A lower electrode(102) is formed on an upper surface of a semiconductor substrate(100). A heating electrode(104) is formed on an upper surface of the lower electrode. An intermediate insulating layer higher than a top part of the heating electrode is formed on a front surface of the semiconductor substrate having the lower electrode and the heating electrode. A buried insulating layer(106a) is formed by planarizing the interlayer dielectric in order to expose the heating electrode. A phase change layer(108) is formed on the heating electrode. An upper electrode(116) is formed on the phase change layer.
Abstract:
A conductive polymer composition, a conductive polymer thin film prepared by using the composition, and an organic electronic device containing the thin film are provided to improve coating property and electrical characteristics. A conductive polymer composition comprises a polythiophene-based conductive polymer aqueous solution; 0.02-5.0 parts by weight of a surface tension controller (surfactant) having both hydrophobicity and hydrophilicity based on the weight of the conductive polymer; and 1-99 parts by weight of a polar solvent. Preferably the polythiophene-based conductive polymer is the poly(3,4-ethylene dioxythiophene) represented by the formula 1 or a mixture of the poly(3,4-ethylene dioxythiophene) represented by the formula 1 and the poly(4-styrene sulfonate) represented by the formula 2, wherein n and m are 5-10,000.
Abstract:
상변화 메모리 소자를 제공한다. 본 발명은 상변화층 패턴을 포함하는 상변화 메모리부와, 상기 상변화 메모리부의 상변화층 패턴에 레이저빔을 국부적으로 집속하는 레이저빔 집속부와, 상기 레이저빔을 발생시켜 상기 레이저빔 집속부로 상기 레이저빔을 방출하는 반도체 레이저부를 포함하여 이루어진다. 이에 따라, 본 발명의 상변화 메모리 소자는 셋 및 리셋 동작시 국부적으로 인가되는 레이저빔을 이용하기 때문에, 소비 전력을 줄이면서도 단위 셀의 동작시에 발생한 열이 인접 셀에 영향을 주어 인접 메모리 셀에 저장된 정보를 파괴하거나 변경시키지 않는다.