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公开(公告)号：KR100925210B1
公开(公告)日：2009-11-06
申请号：KR1020080049053
申请日：2008-05-27
Applicant: 한국전자통신연구원
IPC: H01L21/3065 , H01L29/786
CPC classification number: H01L29/7869 , H01L21/3065 , H01L21/67069
Abstract: PURPOSE: A method for manufacturing an oxide thin film transistor using a dry etching process is provided to prevent the degradation of and an IGZO oxide semiconductor thin film by forming a protecting layer. CONSTITUTION: In a method for manufacturing an oxide thin film transistor using a dry etching process is comprised of the steps: forming a first thin conductive film(203) functioned as a source and a drain electrode at an upper part of a substrate(201); forming an IGZO oxide semiconductor thin film(205) on the first thin conductive films; performing the IGZO oxide semiconductor thin film through a dry etching firstly; performing the IGZO oxide semiconductor thin film through dry etching secondly; forming an insulator film functioned as the gate insulating layer(207) on the IGZO oxide semiconductor thin film; and forming a second thin conductive film(209) functioned as the gate electrode on oxide insulator thin film.
Abstract translation: 目的：提供一种使用干蚀刻工艺制造氧化物薄膜晶体管的方法，以通过形成保护层来防止IGZO氧化物半导体薄膜的劣化。 构成：在使用干蚀刻工艺制造氧化物薄膜晶体管的方法中包括以下步骤：在衬底（201）的上部形成用作源极和漏电极的第一薄导电膜（203） ; 在第一薄导电膜上形成IGZO氧化物半导体薄膜（205）; 首先通过干蚀刻进行IGZO氧化物半导体薄膜; 第二次通过干蚀刻进行IGZO氧化物半导体薄膜; 在IGZO氧化物半导体薄膜上形成用作栅极绝缘层（207）的绝缘膜; 以及形成作为氧化物绝缘体薄膜上的栅电极的第二薄导电膜（209）。
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公开(公告)号：KR1020090099140A
公开(公告)日：2009-09-22
申请号：KR1020080024208
申请日：2008-03-17
Applicant: 한국전자통신연구원
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L21/02554
Abstract: A manufacturing method of a ZnO TFT is provided to reduce a defect inside a semiconductor thin film by controlling a deposition temperature after selecting oxygen plasma or ozone as oxygen precursor. A ZnO semiconductor film(30) is formed on a substrate(10) through an atomic layer deposition method using Zn precursor and ozone at a temperature of 250~350°C or Zn precursor and oxygen plasma at a temperature of 150~250°C. An insulation film(40) is formed on a top part of the ZnO semiconductor film through the atomic layer deposition method using the oxygen precursor selected from ozone or water at a temperature less than 250°C. A gate electrode(50) is formed on a top part of the insulation film. The ZnO semiconductor film has thickness of 5~40nm. The substrate is a substrate in which a source/drain electrode(20) is formed and a substrate in which the gate electrode and the insulation film are formed.
Abstract translation: 提供ZnO薄膜晶体管的制造方法，通过在选择氧等离子体或臭氧作为氧前体后控制沉积温度来减少半导体薄膜内的缺陷。 在250〜350℃的温度下，使用Zn前体和臭氧，在150〜250℃的温度下，通过Zn前体和氧等离子体，通过原子层沉积法在基板（10）上形成ZnO半导体膜（30） 。 通过使用在低于250℃的温度下使用选自臭氧或水的氧前体的原子层沉积方法，在ZnO半导体膜的顶部上形成绝缘膜（40）。 在绝缘膜的顶部形成有栅电极（50）。 ZnO半导体膜的厚度为5〜40nm。 基板是形成源极/漏极（20）的基板和形成有栅电极和绝缘膜的基板。
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公开(公告)号：KR1020090060935A
公开(公告)日：2009-06-15
申请号：KR1020080084534
申请日：2008-08-28
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , C23C16/305 , H01L45/143 , H01L45/144
Abstract: An electronic device using a phase change material, a phase change memory device, and a manufacturing method thereof are provided to make a programmable volume small by generating a phase change layer using a solid state reaction method. An insulation layer covers a first reaction layer in order to form a contact hole which exposes a part of a top part of the first reaction layer(208). A second reaction layer(210) is filled in the contact hole. A phase change layer(215) is formed between the first reaction layer and the second reaction layer. The phase change layer is formed by a solid state reaction of material used in the first reaction layer and material used in the second reaction layer. The phase change layer is made of material which is changed into an amorphous state and a crystalline state according to a current amount.
Abstract translation: 提供了使用相变材料的电子设备，相变存储器件及其制造方法，通过使用固态反应方法生成相变层来使可编程体积小。 绝缘层覆盖第一反应层以形成暴露第一反应层（208）顶部的一部分的接触孔。 第二反应层（210）填充在接触孔中。 在第一反应层和第二反应层之间形成相变层（215）。 相变层通过第一反应层中使用的材料和第二反应层中使用的材料的固态反应形成。 相变层由根据电流量变为非晶状态和结晶状态的材料制成。
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公开(公告)号：KR100889743B1
公开(公告)日：2009-03-24
申请号：KR1020060124118
申请日：2006-12-07
Applicant: 한국전자통신연구원
IPC: H01L27/115
CPC classification number: H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1666
Abstract: 본 발명에 따른 상변화 메모리는 반도체 기판 위의 게이트 전극 및 상기 게이트 전극 양 옆으로 상기 반도체 기판에 형성된 제1 및 제2 불순물 영역을 포함하는 트랜지스터; 상기 제1 불순물 영역과 전기적으로 연결되는 비트라인; 및 상기 제2 불순물 영역과 전기적으로 연결되는 상변화 저항소자를 포함하되, 상기 상변화 저항소자는 도핑된 SiGe 층으로 형성된 하부 전극; 상기 하부 전극과 접촉하는 상변화층; 및 상기 상변화층과 연결된 상부 전극을 포함한다.
하부 전극으로 비저항이 높고, 열전도도가 낮은 도핑된 SiGe 를 채용함으로써 리셋 전류를 줄일 수 있고, 상변화 메모리 전체의 전력 소모를 줄일 수 있다.
상변화 메모리, 리셋 전류, 하부 전극, SiGe-
公开(公告)号：KR100884357B1
公开(公告)日：2009-02-17
申请号：KR1020070094552
申请日：2007-09-18
Applicant: 한국전자통신연구원
IPC: H01L29/786
CPC classification number: H01L51/052
Abstract: An organic gate insulating layer and an organic thin film transistor are provided to minimize influence on other film by the organic gate insulating layer by forming the organic gate insulating layer with low permittivity, high chemical and thermal stability, and low absorption rate at a low temperature. A source electrode, a drain electrode and a gate electrode(20) are positioned on a surface of a substrate(10). An organic gate insulating layer(30) is interposed between the source electrode and the gate electrode and between the drain electrode and the gate electrode. The organic gate insulating layer includes polysiloxane or polysiloxane derivative. An organic active film contacts the organic gate insulating layer. The source electrode and the drain electrode are connected by the organic active film.
Abstract translation: 提供有机栅极绝缘层和有机薄膜晶体管，以通过形成具有低介电常数，高化学和热稳定性以及低温下的低吸收率的有机栅极绝缘层来最小化由有机栅极绝缘层对其它膜的影响 。 源电极，漏电极和栅电极（20）位于基板（10）的表面上。 在源电极和栅电极之间以及漏电极和栅电极之间插入有机栅极绝缘层（30）。 有机栅绝缘层包括聚硅氧烷或聚硅氧烷衍生物。 有机活性膜与有机栅极绝缘层接触。 源电极和漏电极通过有机活性膜连接。
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Patent Agency Ranking
公开(公告)号：KR100833505B1
公开(公告)日：2008-05-29
申请号：KR1020060122600
申请日：2006-12-05
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1666 , H01L45/1691
Abstract: A phase change memory device which has a small contact between a phase change layer and a heating electrode, and a manufacturing method thereof are provided to decrease contact size and reset current by forming the heating electrode which has an upper end shorter than a lower end. The plural lower part electrodes(102a,102b) are formed on a semiconductor substrate(100). The plural heating electrodes(112a,112b) which have lower ends of shorter length than upper ends are formed on the lower electrodes. The plural phase change layers(114a,114b) are formed adjacent to the upper end of the heating electrode. The plural upper part electrodes(124a,124b) are formed on the phase change layers.
Abstract translation: 提供了相变层和加热电极之间具有小接触的相变存储器件及其制造方法，其通过形成上端短于下端的加热电极来减小接触尺寸和复位电流。 多个下部电极（102a，102b）形成在半导体衬底（100）上。 在下部电极上形成多个长度比上端短的端部的加热电极（112a，112b）。 多个相变层（114a，114b）与加热电极的上端相邻地形成。 在相变层上形成多个上部电极（124a，124b）。
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公开(公告)号：KR100825767B1
公开(公告)日：2008-04-29
申请号：KR1020070043800
申请日：2007-05-04
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: A PRAM(Phase change RAM) device and a method for manufacturing the same are provided to enhance reliability by using a heat-radiating layer having an optimum heat-radiating characteristic. A PRAM device comprises a lower electrode(110) formed on a semiconductor substrate, an upper electrode(150) formed on the lower electrode, and a PRAM layer formed between the lower electrode and the upper electrode. A heat-radiating layer(120) is formed between the upper electrode or the lower electrode and the PRAM. The heat-radiating layer includes a first heat-radiating layer(121) and a second heat-radiating layer(122). The first heat-radiating layer comes in contact with the PRAM layer. The second heat-radiating layer comes in contact with the first heat-radiating layer and is positioned between the first heat-radiating layer and the upper electrode or the lower electrode.
Abstract translation: 提供PRAM（相变RAM）装置及其制造方法，以通过使用具有最佳散热特性的散热层来提高可靠性。 PRAM器件包括形成在半导体衬底上的下电极（110），形成在下电极上的上电极（150）和形成在下电极和上电极之间的PRAM层。 在上电极或下电极与PRAM之间形成散热层（120）。 散热层包括第一散热层（121）和第二散热层（122）。 第一散热层与PRAM层接触。 第二散热层与第一散热层接触并位于第一散热层与上电极或下电极之间。
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公开(公告)号：KR100785807B1
公开(公告)日：2007-12-13
申请号：KR1020060122550
申请日：2006-12-05
Applicant: 한국전자통신연구원
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: A method of fabricating a phase change memory device for obtaining high integration without a gap fill process is provided to reduce a manufacturing cost by reducing the number of processes without increasing the gap-fill process. A lower electrode(102) is formed on an upper surface of a semiconductor substrate(100). A heating electrode(104) is formed on an upper surface of the lower electrode. An intermediate insulating layer higher than a top part of the heating electrode is formed on a front surface of the semiconductor substrate having the lower electrode and the heating electrode. A buried insulating layer(106a) is formed by planarizing the interlayer dielectric in order to expose the heating electrode. A phase change layer(108) is formed on the heating electrode. An upper electrode(116) is formed on the phase change layer.
Abstract translation: 提供一种制造用于在没有间隙填充处理的情况下获得高集成度的相变存储器件的方法，以通过在不增加间隙填充处理的情况下减少工艺数量来降低制造成本。 在半导体衬底（100）的上表面上形成下电极（102）。 在下电极的上表面上形成加热电极（104）。 在具有下电极和加热电极的半导体衬底的前表面上形成高于加热电极顶部的中间绝缘层。 通过使层间电介质平坦化以使加热电极露出而形成掩埋绝缘层（106a）。 在加热电极上形成相变层（108）。 上电极（116）形成在相变层上。
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公开(公告)号：KR100772926B1
公开(公告)日：2007-11-02
申请号：KR1020060094046
申请日：2006-09-27
Applicant: 한국전자통신연구원
Abstract: A conductive polymer composition, a conductive polymer thin film prepared by using the composition, and an organic electronic device containing the thin film are provided to improve coating property and electrical characteristics. A conductive polymer composition comprises a polythiophene-based conductive polymer aqueous solution; 0.02-5.0 parts by weight of a surface tension controller (surfactant) having both hydrophobicity and hydrophilicity based on the weight of the conductive polymer; and 1-99 parts by weight of a polar solvent. Preferably the polythiophene-based conductive polymer is the poly(3,4-ethylene dioxythiophene) represented by the formula 1 or a mixture of the poly(3,4-ethylene dioxythiophene) represented by the formula 1 and the poly(4-styrene sulfonate) represented by the formula 2, wherein n and m are 5-10,000.
Abstract translation: 提供导电聚合物组合物，通过使用该组合物制备的导电聚合物薄膜和含有薄膜的有机电子器件以改善涂层性能和电特性。 导电聚合物组合物包含聚噻吩基导电聚合物水溶液; 基于导电聚合物的重量，0.02-5.0重量份具有疏水性和亲水性的表面张力控制剂（表面活性剂）; 和1-99重量份的极性溶剂。 优选地，聚噻吩基导电聚合物是由式1表示的聚（3,4-亚乙基二氧噻吩）或由式1表示的聚（3,4-亚乙基二氧噻吩）与聚（4-苯乙烯磺酸盐） ），其中n和m为5-10,000。
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公开(公告)号：KR100753842B1
公开(公告)日：2007-08-31
申请号：KR1020060085826
申请日：2006-09-06
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
Abstract: 상변화 메모리 소자를 제공한다. 본 발명은 상변화층 패턴을 포함하는 상변화 메모리부와, 상기 상변화 메모리부의 상변화층 패턴에 레이저빔을 국부적으로 집속하는 레이저빔 집속부와, 상기 레이저빔을 발생시켜 상기 레이저빔 집속부로 상기 레이저빔을 방출하는 반도체 레이저부를 포함하여 이루어진다. 이에 따라, 본 발명의 상변화 메모리 소자는 셋 및 리셋 동작시 국부적으로 인가되는 레이저빔을 이용하기 때문에, 소비 전력을 줄이면서도 단위 셀의 동작시에 발생한 열이 인접 셀에 영향을 주어 인접 메모리 셀에 저장된 정보를 파괴하거나 변경시키지 않는다.
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