-
公开(公告)号：KR1019930007050B1
公开(公告)日：1993-07-26
申请号：KR1019900021862
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The snoop controller provides a pended bus protocol which enables data to be read always correctly in multiple processors. It includes comparators (4,5) for comparing the address from a bus with the contents of an internal tag comparator (7) and a status memory (8), and a decoder (2) for applying SNACK signal to the bus to provide the time for cache coherence when the result of the comparator (5) is true.
Abstract translation: 监听控制器提供了一种挂起总线协议，使得数据可以在多个处理器中始终正确读取。 它包括用于将来自总线的地址与内部标签比较器（7）和状态存储器（8）的内容进行比较的比较器（4,5），以及用于将SNACK信号施加到总线以提供 当比较器（5）的结果为真时，缓存一致性的时间。
-
-
公开(公告)号：KR1019920002663B1
公开(公告)日：1992-03-31
申请号：KR1019890019312
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: The apparatus includes a data transmission bus requestor (2) for carrying out data transmissions and for informing it to a processor (1). A responder (2) transfers the task to a memory (4), and informs the result to the data transmission bus requestor (2). An address region encoder (12) forms an address region in accordance with the output of the processor (1), and a parity generator (13) generates parity signals for data transmissions. A slot address translator (14) generates address tags, and a tag receiver (20) receives the address tags through the system bus (3). A comparator (21) compares the address tags with the data tags. The apparatus maximizes the utilization of the system bus.
Abstract translation: 该装置包括用于执行数据传输并将其通知给处理器（1）的数据传输总线请求器（2）。 响应者（2）将任务传送到存储器（4），并将结果通知给数据传输总线请求者（2）。 地址区域编码器（12）根据处理器（1）的输出形成地址区域，并且奇偶生成器（13）产生用于数据传输的奇偶校验信号。 插槽地址转换器（14）产生地址标签，标签接收器（20）通过系统总线（3）接收地址标签。 比较器（21）将地址标签与数据标签进行比较。 该装置使系统总线的利用最大化。
-
-
-
Patent Agency Ranking
公开(公告)号：KR100452325B1
公开(公告)日：2004-10-12
申请号：KR1020020082895
申请日：2002-12-23
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.
Abstract translation: 目的：提供AMBA（高级微控制器总线架构）总线多处理器系统来分配处理器编号并被顺序引导，以便轻松实现基于共享总线的多处理器系统，并能够在稍后安装多处理器OS（操作系统） 通过分配处理器ID并依次引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和写数据信号线，将主设备（210-1和210-3）与其他资源连接起来。 总线仲裁器（230）根据总线使能信号通过接收来自主设备的总线请求信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主设备的总线使用许可，并且输出总线用户 接收总线使用权限的主设备号码。 支持从设备（280）的多处理器向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线使用者号码。
-
公开(公告)号：KR100445427B1
公开(公告)日：2004-08-25
申请号：KR1020020077571
申请日：2002-12-07
Applicant: 한국전자통신연구원
IPC: G06N3/12
CPC classification number: G06N99/005
Abstract: The present invention relates to a radial basis function classifier generating system and method to classify gene expression pattern appearing on micro-array for functional property. In the present invention, the 'representation coverage' to be represented by classifier and the 'representation precision', instead of various variables, are set to be input variables and other variables required to generate classifier are automatically determined based on the given values of the input variables. Developer's selection of the values of variables is minimized and the unnecessary trial-and-errors are reduced. Developers understand easily meaning of such input variables and can predict the result of the selection of variables. Accordingly, the trial-and-errors due to meaningless selection of the values of the variables are reduced, so the classifier generation process can be optimized.
Abstract translation: 本发明涉及一种径向基函数分类器生成系统和方法，用于对出现在微阵列上的基因表达模式进行分类以获得功能特性。 在本发明中，代替各种变量，将要由分类器表示的'表示覆盖率'和'表示精度'被设置为输入变量，并且基于给定值的值来自动确定生成分类器所需的其他变量 输入变量。 开发人员对变量值的选择被最小化，并减少了不必要的试错。 开发人员很容易理解这些输入变量的含义，并可以预测变量选择的结果。 因此，由于无意义地选择变量的值而导致的试错被减少，所以分类器生成过程可以被优化。
-
公开(公告)号：KR1020040056293A
公开(公告)日：2004-06-30
申请号：KR1020020082895
申请日：2002-12-23
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.
Abstract translation: 目的：提供用于分配处理器号并被顺序启动的基于总线架构的AMBA（高级微控制器总线体系结构）总线系统，以便轻松实现基于共享总线的多处理器系统，并且可以稍后安装多处理器OS（操作系统） 通过分配处理器ID并顺序引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和连接主机（210-1〜210-3）与其他资源的写数据信号线。 总线仲裁器（230）通过从主机接收总线请求信号，根据总线使能信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主机的总线使用许可，并输出总线用户 接收总线使用许可的主机号码。 多处理器支持从站（280）向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线用户号码。
-
公开(公告)号：KR1020040055194A
公开(公告)日：2004-06-26
申请号：KR1020020081819
申请日：2002-12-20
Applicant: 한국전자통신연구원
IPC: G06F13/00
CPC classification number: G06F13/28
Abstract: PURPOSE: A system for controlling a data transfer protocol having a host bus interface is provided to support the optimal data transfer through the efficient use of a host interface bus and the proper distribution of a bus use rate, and smoothly process entire data transfer by controlling a host bus and the data transfer protocol. CONSTITUTION: The system includes a data transfer protocol controller(130), a transmitting/receiving command DMA(Direct Memory Access)(140), a transmitting-only data DMA(150), and a receiving-only data DMA(160). The data transfer protocol controller controls the data transfer protocol in a host channel adaptor having a PCI(Peripheral Component Interconnect)/PCI-X host bus interface(120) of a PCI/PCI-X host bus(110) as a host processor interface, and is equipped with a protocol processing master(131), an interrupt controller(132), and a protocol processing target(133). The system includes a command DMA request buffer(141), a command DMA response DMA buffer(142), a transmitting data DMA request buffer(151), a transmitting data DMA response buffer(152), a receiving data DMA request buffer(161), and a receiving data DMA response buffer(162).
Abstract translation: 目的：提供一种用于控制具有主机总线接口的数据传输协议的系统，以通过有效使用主机接口总线和正确分配总线使用率来支持最佳数据传输，并通过控制来平滑地处理整个数据传输 主机总线和数据传输协议。 构成：该系统包括数据传输协议控制器（130），发送/接收命令DMA（直接存储器访问）（140），只发送数据DMA（150）和仅接收数据DMA（160）。 数据传输协议控制器控制具有作为主处理器接口的PCI / PCI-X主机总线（110）的PCI（外围组件互连）/ PCI-X主机总线接口（120）的主机通道适配器中的数据传输协议 ，并配备有协议处理主控（131），中断控制器（132）和协议处理对象（133）。 该系统包括命令DMA请求缓冲器（141），命令DMA响应DMA缓冲器（142），发送数据DMA请求缓冲器（151），发送数据DMA响应缓冲器（152），接收数据DMA请求缓冲器（161） ）和接收数据DMA响应缓冲器（162）。
-
公开(公告)号：KR1020040037989A
公开(公告)日：2004-05-08
申请号：KR1020020066844
申请日：2002-10-31
Applicant: 한국전자통신연구원
IPC: G11C7/00
CPC classification number: G11C8/04
Abstract: PURPOSE: A first input first output(FIFO) memory circuit and a method for implementing the same are provided to improve the input and output speed of the FIFO memory by controlling the low speed memory. CONSTITUTION: A first input first output memory circuit includes a memory(100), a read pointer(400), a write pointer(300) and a memory controller(200). The memory(100) is composed of N number of memories. The read pointer(400) appoints the read address among the N number of memories and the write pointer(300) appoints the write address among the N number of memories. And, the memory controller(200) selects one memory among the N number of memories in response to the read/write address, generates a source clock signal by the divided n number of read/write clock signal and inputs and outputs the data by dividing the n number of read/write clock signal from the selected memory to the corresponding memory.
Abstract translation: 目的：提供第一输入第一输出（FIFO）存储器电路及其实现方法，以通过控制低速存储器来提高FIFO存储器的输入和输出速度。 构成：第一输入第一输出存储电路包括存储器（100），读指针（400），写指针（300）和存储器控制器（200）。 存储器（100）由N个存储器构成。 读指针（400）在N个存储器中指定读地址，写指针（300）在N个存储器中指定写地址。 并且，存储器控制器（200）响应于读/写地址在N个存储器中选择一个存储器，通过分割的n个读/写时钟信号产生源时钟信号，并通过分割来输入和输出数据 从所选择的存储器到对应的存储器的n个读/写时钟信号。
-
-
-
-
-
-
-
-
-
Search Results
107
records
(took 0.02 seconds)
