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    82.
    发明专利
    未知

    公开(公告)号：DE59902762D1

    公开(公告)日：2002-10-24

    申请号：DE59902762

    申请日：1999-03-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

    IPC: G06F7/50 ,  G06F7/52 ,  H01L29/66 ,  H03K19/08

    Abstract: The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply voltage, with its gate electrode being connected to the first main node. The fifth single-electron transistor is connected between the third main node and the first supply voltage, with its gate electrode being connected to the second main node. The circuit configuration is suitable for use as a full adder and as a multiplier.

    85.
    发明专利
    未知

    公开(公告)号：DE59804805D1

    公开(公告)日：2002-08-22

    申请号：DE59804805

    申请日：1998-03-11

    Applicant: INFINEON TECHNOLOGIES AG ,  UNIV RUHR BOCHUM

    Inventor： AEUGLE THOMAS ,  ROESNER WOLFGANG ,  BEHAMMER DAG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which essentially covers the side walls of the lower source/drain region. A gate dielectric and a gate electrode, whose height is essentially equal to the height of the channel region, are formed on the side walls of the channel region.

    87.
    发明专利
    未知

    公开(公告)号：DE59804346D1

    公开(公告)日：2002-07-11

    申请号：DE59804346

    申请日：1998-09-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RAMCKE TIES ,  ROESNER WOLFGANG ,  RISCH LOTHAR

    IPC: G11C11/15 ,  G11C11/16 ,  G11C15/02 ,  G11C15/04 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

    Abstract: A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

    88.
    发明专利
    未知

    公开(公告)号：DE59901323D1

    公开(公告)日：2002-06-06

    申请号：DE59901323

    申请日：1999-01-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KRAUTSCHNEIDER WOLFGANG ,  RISCH LOTHAR ,  HOFMANN FRANZ ,  ROESNER WOLFGANG

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: The memory cell has a capacitor electrode (Sk), provided at its flanks with a capacitor dielectric (Kd), with the bit line (B2) coupled to the storage capacitor (Ko) acting as the second capacitor electrode. The first capacitor electrode is surrounded in a ring by the capacitor dielectric, with a selection transistor positioned beneath the capacitor and connected to the first capacitor electrode. The transistor may be positioned between the capacitor and a second bit line.

    89.
    发明专利
    未知

    公开(公告)号：DE19928564A1

    公开(公告)日：2001-01-04

    申请号：DE19928564

    申请日：1999-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  FRANOSCH MARTIN

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/788

    Abstract: A dual-gate MOSFET semiconductor layer structure is constructed on a substrate (1). Said semiconductor layer structure consists of a first gate electrode and a second gate electrode (10A, 10B), between which a semiconductor channel layer area (4A) is embedded, and a source area (2A) and a drain area (2B), which are situated on opposite front sides of the semiconductor channel layer area (4A). At least one other semiconductor channel layer area (6A) is provided at one of the gate electrodes (10B), the front sides of this semiconductor channel layer area (6A) also being contacted by the source (2A) and drain (2B) areas.

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