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    81.
    发明专利
    未知

    公开(公告)号：DE69422794D1

    公开(公告)日：2000-03-02

    申请号：DE69422794

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  PASCUCCI LUIGI

    IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177

    Abstract: The PLA (1), which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator (30) which generates a monostable succession of read enabling signals (CPPA, CPPO, CPM) on receiving a predetermined switching edge of an external clock signal (CP). The clock generator enables evaluation of the AND (3) and OR (4) planes of the PLA and subsequently storage of the results through sections (33, 38; 48) duplicating the propagation delays of the signals in the corresponding parts (3-5) of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

    82.
    发明专利
    未知

    公开(公告)号：DE69419403T2

    公开(公告)日：1999-12-30

    申请号：DE69419403

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

    Abstract: A load timing circuit (20) including an out-like circuit (21) identical to the output circuits of the memory, so as to present the same propagation time; a simulating signal source (34) for generating a data simulating signal (SP); a synchronizing network (30, 32) for detecting a predetermined switching edge of the data simulating signal (SP) and enabling (35) supply of the signal to the out-like circuit (21) and data supply to the output circuits of the memory; a combinatorial network (29, 30) for detecting propagation of the data simulating signal (SP) to the output of the out-like circuit and disabling the data simulating signal (SP); and a reset element (33) for resetting the timing circuit (20).

    83.
    发明专利
    未知

    公开(公告)号：ITMI992480D0

    公开(公告)日：1999-11-26

    申请号：ITMI992480

    申请日：1999-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10

    Abstract: An output buffer, particularly for non-volatile memories, includes a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage. The first and second circuits for disabling the push-pull stage may be respectively connected between the first and second activation paths and the first data latch circuit and may receive as inputs an output enable signal and a data updating signal. Additionally, the second and third data latch circuits may be connected between the push-pull stage and, respectively, the first and second activation paths for the activation of the push-pull stage.

    84.
    发明专利
    未知

    公开(公告)号：DE69326154D1

    公开(公告)日：1999-09-30

    申请号：DE69326154

    申请日：1993-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G06F11/20

    Abstract: An integrated circuit for the programming of a memory cell in a non-volatile memory register, said memory cell comprising at least one programmable non-volatile memory element (TF;TF0,TF1) having a cotrol electrode and a supply electrode and being suitable to store one bit of information and a load circuit (LC;T0-T3) associated to said memory element (TF;TF0,TF1) to read the information stored therein, comprises switching means (TS;T4,T5), connected in series between the supply electrode of said at least one memory element (TF;TF0,TF1) and a respective data line (A;A,AN) carrying a datum to be programmed into said memory element (TF;TF0,TF1); the switching means are controlled by a signal (7) which determines the switching means (TS;T4,T5) to electrically connect the memory element (TF;TF0,TF1) to the data line (A;A,AN) when the memory cell of the non-volatile memory register is to be programmed.

    85.
    发明专利
    未知

    公开(公告)号：DE69412234D1

    公开(公告)日：1998-09-10

    申请号：DE69412234

    申请日：1994-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  CARRERA MARCELLO ,  DEFENDI MARCO

    IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G06F11/20

    Abstract: A Redundancy circuitry layout for a semiconductor memory device comprises an array (MAR) of programmable non-volatile memory elements (TF0,TF1) for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines; the redundancy circuitry layout is divided in identical layout strips (LS1-LS4) which are perpendicular to the array (MAR) of memory elements (TF0,TF1) and which comprise each a first and a second strip sides located at opposite sides of the array (MAR) of memory elements (TF0,TF1), the first strip side containing at least one programmable non-volatile memory register (CRRA,CRRB) of a first plurality for the selection of redundancy bit lines and being crossed by a column address signal bus (CABUS) running parallel to the array (MAR of memory elements (TF0,TF1), the second strip side containing one programmable non-volatile memory register (RRR) of a second plurality for the selection of redundancy word lines and being crossed by a row address signal bus (RABUS) running parallel to the array (MAR) of memory elements (TF0,TF1).

    89.
    发明专利
    未知

    公开(公告)号：DE60042272D1

    公开(公告)日：2009-07-09

    申请号：DE60042272

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C8/04

    Abstract: Internal addressing structure for a semiconductor memory with at least two memory banks, comprising a counter (61,62) associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, first circuit means (75,76) for causing a selective updating of the counters, second circuit means (71,72,IN_A) for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus (ADD), corresponding to an initial memory location, and third circuit means (77,71,72) capable of detecting a first signal (ALE), supplied to the memory from the outside and indicating the presence of a digital code on the said bus, to cause the said common initial digital code to be loaded into the counters. The said first circuit means are capable of identifying, on the basis of the said initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the said initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.

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