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公开(公告)号：KR101531181B1
公开(公告)日：2015-06-25
申请号：KR1020080102948
申请日：2008-10-21
Applicant: 삼성전자주식회사
IPC: H01L23/12 , H01L23/48 , H01L23/045
CPC classification number: H01L2224/13 , H01L2924/01029 , H01L2924/01047 , H01L2924/014
Abstract: 적층패키지는제1 반도체칩, 범프및 제2 반도체칩을포함한다. 상기제1 반도체칩은개구를갖는기판및 상기개구를채우면서상부에리세스를갖는플러그를구비한다. 상기범프는상기리세스내에형성된다. 상기제2 반도체칩은상기제1 반도체칩 상에적층되며상기범프에의해상기제1 반도체칩과전기적으로연결된다.
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公开(公告)号：KR1020120058114A
公开(公告)日：2012-06-07
申请号：KR1020100119757
申请日：2010-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L23/48 , H01L25/065 , H01L23/525
CPC classification number: H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
Abstract: PURPOSE: A semiconductor device, a manufacturing method thereof, and a semiconductor package including the same are provided to prevent a semiconductor substrate and a penetrating electrode to be shorted by preventing the damage of a via hole insulating layer when eliminating a first insulating layer of penetrating via. CONSTITUTION: A semiconductor substrate(10) comprises a first side(11) and a second side(12) opposed to the first side. An integrated circuit(13) is formed on the first side of the semiconductor substrate. A via hole(16) is separated from the integrated circuit and is provided within the semiconductor substrate. A penetrating electrode(20) comprises a conductive connection unit(26) and a barrier layer(24). The barrier layer is formed at the inner wall of the via hole. A trench(103) is formed at the second side of the semiconductor substrate. A re-wire(45) is electrically connected with the penetrating electrode.
Abstract translation: 目的：提供一种半导体器件及其制造方法以及包含该半导体器件的半导体封装，以防止半导体衬底和穿透电极在消除穿透绝缘层的第一绝缘层时通过防止通孔绝缘层的损坏来短路 通过。 构成：半导体衬底（10）包括与第一侧相对的第一侧（11）和第二侧（12）。 在半导体衬底的第一侧上形成集成电路（13）。 通孔（16）与集成电路分离并设置在半导体衬底内。 穿透电极（20）包括导电连接单元（26）和阻挡层（24）。 阻挡层形成在通孔的内壁。 沟槽（103）形成在半导体衬底的第二侧。 再线（45）与穿透电极电连接。
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公开(公告)号：KR101604607B1
公开(公告)日：2016-03-18
申请号：KR1020090101623
申请日：2009-10-26
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L21/76898 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 반도체장치의제조방법에있어서, 제1 면및 상기제1 면에반대하는제2 면을갖는기판을마련한다. 상기기판의상기제2 면상에제1 절연막을형성한다. 상기제1 절연막상에희생막을형성한다. 상기기판을관통하며상기제1 면으로부터상기희생막의일부까지연장된개구를형성한다. 상기개구의내벽상에제2 절연막을형성한다. 상기개구를채우는플러그를형성한다. 상기희생막을제거하여상기플러그의하부를상기제2 면으로부터노출시킨다. 상기플러그의하부를노출시키는단계이전에상기기판의제1 면은상기제1 절연막에의해이미도포되어있고, 상기제2 접속부의외측벽은상기제2 절연막에의해이미도포되어있다. 따라서, 이후의식각공정등과같은공정들을수행할때, 구리와같은상기플러그의금속이상기기판내부로확산되는것을방지하여상기반도체장치의전기적신뢰성을향상시킬수 있게된다.
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公开(公告)号：KR1020110091333A
公开(公告)日：2011-08-11
申请号：KR1020100011117
申请日：2010-02-05
Applicant: 삼성전자주식회사
CPC classification number: H01L25/0657 , H01L21/561 , H01L21/563 , H01L23/481 , H01L23/49816 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555
Abstract: PURPOSE: A multichip package having semiconductor chips of different thickness each other and a related device are provided to reduce reliability deterioration by improving coefficient of thermal expansion mismatch and thermal history. CONSTITUTION: In a multichip package having semiconductor chips of different thickness each other and a related device, one or a plurality of semiconductor chips are laminated on a semiconductor chip and has a plurality penetrating electrodes. An external connection terminal is included in the surface of selected one semiconductor chips and is passed through the penetrating electrode to be electrically connected to the semiconductor chip or a thin semiconductor chip.
Abstract translation: 目的：提供具有不同厚度的半导体芯片的多芯片封装以及相关的器件，以通过改善热膨胀失配和热历史的系数来降低可靠性劣化。 构成：在具有不同厚度的半导体芯片的多芯片封装和相关器件中，一个或多个半导体芯片层压在半导体芯片上并具有多个穿透电极。 外部连接端子被包括在所选择的一个半导体芯片的表面中，并且穿过贯通电极以与半导体芯片或薄的半导体芯片电连接。
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公开(公告)号：KR1020110045185A
公开(公告)日：2011-05-04
申请号：KR1020090101623
申请日：2009-10-26
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L21/76898 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/3025 , H01L23/48 , H01L23/12 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor device and manufacturing method thereof are provided to suppress spreading of a metal material penetrating a semiconductor chip, thereby enhancing electrical features. CONSTITUTION: A substrate(10) comprises a first surface(12) and a second surface(14) opposite to the first surface. A plurality of chip pads(20) is formed on the first surface of the substrate. A plug(70) comprises a first connection unit exposed from the first surface and a second connection unit exposed from the second surface. A first insulating film(30) is formed on the second surface. A second insulating layer(60) is formed on the external surfaces of the plug in the substrate and the second connection unit.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以抑制穿透半导体芯片的金属材料的扩散，从而增强电气特征。 构成：衬底（10）包括与第一表面相对的第一表面（12）和第二表面（14）。 在基板的第一表面上形成多个芯片焊盘（20）。 插头（70）包括从第一表面露出的第一连接单元和从第二表面露出的第二连接单元。 在第二表面上形成第一绝缘膜（30）。 第二绝缘层（60）形成在基板和第二连接单元中的插头的外表面上。
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Patent Agency Ranking
公开(公告)号：KR101697573B1
公开(公告)日：2017-01-19
申请号：KR1020100119757
申请日：2010-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L23/48 , H01L25/065 , H01L23/525
CPC classification number: H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
Abstract: 반도체장치, 그제조방법, 및상기반도체장치를포함하는반도체패키지가제공된다. 반도체장치는제1 면, 및상기제1 면과반대되며트렌치가형성된제2 면을갖는기판, 상기기판내에형성된비아홀을채우며상기비아홀의내벽으로부터순차적으로형성된비아홀절연막, 배리어막, 및도전성연결부를포함하는관통비아, 상기제2 면상에형성되며상기관통비아의일정영역을노출하는절연막, 및상기트렌치내에매립되며, 상기관통비아와전기적으로연결되는재배선을포함하되, 상기절연막은상기도전성연결부의일정영역과중첩한다.
Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。
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公开(公告)号：KR1020120067694A
公开(公告)日：2012-06-26
申请号：KR1020100129238
申请日：2010-12-16
Applicant: 삼성전자주식회사
IPC: H01L23/498 , H01L23/31 , H01L21/768 , H01L23/00 , H01L21/683 , H01L25/065 , H01L27/146 , H01L21/48
CPC classification number: H01L21/4835 , H01L21/6836 , H01L21/76898 , H01L23/3114 , H01L23/3192 , H01L23/49827 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/14618 , H01L2221/68327 , H01L2221/6834 , H01L2224/02166 , H01L2224/02313 , H01L2224/02372 , H01L2224/02375 , H01L2224/02381 , H01L2224/024 , H01L2224/03462 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32225 , H01L2224/45139 , H01L2224/48105 , H01L2224/48227 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L21/62 , H01L21/67 , H01L21/67005 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to increase insulating properties by placing an organic insulating pattern between rewiring patterns and to prevent metal to be diffused into the organic insulating pattern through a seed layer pattern. CONSTITUTION: A through via(9a) passes through a semiconductor substrate. First rewiring patterns(29a, 29b) are electrically connected with the through via. A first organic insulating pattern(25) is placed between the first rewiring patterns. The thickness of the first organic insulating pattern is over 2micrometers. First seed layer patterns(27a, 27b) are placed between the first organic insulating pat and the first rewiring patterns. A first seed layer pattern is placed between the first rewiring patterns and the semiconductor substrate. A first passivation layer covers the first rewiring patterns.
Abstract translation: 目的：提供一种半导体器件及其制造方法，通过在重新布线图案之间放置有机绝缘图案并防止金属通过晶种层图案扩散到有机绝缘图案中来增加绝缘性能。 构成：通孔（9a）穿过半导体衬底。 第一重新布线图案（29a，29b）与通孔电连接。 第一有机绝缘图案（25）被放置在第一重新布线图案之间。 第一有机绝缘图案的厚度超过2微米。 第一种子层图案（27a，27b）被放置在第一有机绝缘pat和第一重新布线图案之间。 第一种子层图案被放置在第一重新布线图案和半导体衬底之间。 第一钝化层覆盖第一重新布线图案。
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公开(公告)号：KR1020120020553A
公开(公告)日：2012-03-08
申请号：KR1020100084224
申请日：2010-08-30
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76898
Abstract: PURPOSE: A semiconductor chip and a method for forming a semiconductor chip are provided to uniformly maintain the thickness of a semiconductor chip by etching the back side of a semiconductor chip by using an insulating layer included in the substrate as an etch stopping layer. CONSTITUTION: A semiconductor layer(105) has an active surface(10) and an non-active layer(20) which face each other. A first inter layer dielectric layer(110) is formed on the active surface of the semiconductor layer. An insulating layer(103) is arranged on the non-active layer of the semiconductor layer. A through hole(115) successively passes through the first inter layer dielectric layer, the semiconductor layer, and the insulating layer. A spacer(125) is interposed between the inner wall of the hole and a through electrode.
Abstract translation: 目的：提供一种半导体芯片和半导体芯片的形成方法，通过使用包含在基板中的绝缘层作为蚀刻停止层，通过蚀刻半导体芯片的背面来均匀地保持半导体芯片的厚度。 构成：半导体层（105）具有彼此面对的有源表面（10）和非有源层（20）。 在半导体层的有源表面上形成第一层间介电层（110）。 绝缘层（103）布置在半导体层的非有源层上。 通孔115依次通过第一层间介电层，半导体层和绝缘层。 间隔物（125）插入在孔的内壁和贯通电极之间。
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公开(公告)号：KR101789765B1
公开(公告)日：2017-11-21
申请号：KR1020100129238
申请日：2010-12-16
Applicant: 삼성전자주식회사
IPC: H01L23/498 , H01L23/31 , H01L21/768 , H01L23/00 , H01L21/683 , H01L25/065 , H01L27/146 , H01L21/48
CPC classification number: H01L21/4835 , H01L21/6836 , H01L21/76898 , H01L23/3114 , H01L23/3192 , H01L23/49827 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/14618 , H01L2221/68327 , H01L2221/6834 , H01L2224/02166 , H01L2224/02313 , H01L2224/02372 , H01L2224/02375 , H01L2224/02381 , H01L2224/024 , H01L2224/03462 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32225 , H01L2224/45139 , H01L2224/48105 , H01L2224/48227 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
Abstract: 본발명은반도체장치및 이의제조방법을제공한다. 이반도체장치에서는, 재배선패턴들사이에유기절연패턴이개재된다. 상기재배선패턴이열에의해팽창될경우발생되는물리적스트레스를상기유기절연패턴이흡수할수 있다. 이로써유연성을증대시킬수 있다. 재배선패턴들사이에유기절연패턴이개재되므로, 재배선패턴들사이에반도체패턴이개재되는경우에비해, 절연성을증대시킬수 있다. 또한재배선패턴과유기절연패턴사이그리고반도체기판과유기절연패턴사이에시드막패턴이개재되므로, 재배선패턴의접착력이향상되어박리문제를개선할수 있다. 또한재배선패턴을구성하는금속이유기절연패턴으로확산되는것을시드막패턴이방지할수 있다. 이로써, 신뢰성이향상된반도체장치를구현할수 있다.
Abstract translation: 本发明提供了一种半导体器件及其制造方法。 在该半导体器件中，有机绝缘图案插入再分布图案之间。 有机绝缘图案可以吸收重新布线图案因热而膨胀时产生的物理应力。 这可以增加灵活性。 由于有机绝缘图案介于再布线图案之间，因此与在再布线图案之间插入半导体图案的情况相比，可以增加绝缘性。 另外，由于种子膜图案介于再布线图案和有机绝缘图案之间以及半导体基板和有机绝缘图案之间，因此再布线图案的附着性得到改善并且可以解决剥离问题。 也可以防止籽晶膜图案将构成再布线图案的金属扩散到有机绝缘图案中。 结果，可以实现具有改进的可靠性的半导体器件。
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公开(公告)号：KR101624972B1
公开(公告)日：2016-05-31
申请号：KR1020100011117
申请日：2010-02-05
Applicant: 삼성전자주식회사
CPC classification number: H01L25/0657 , H01L21/561 , H01L21/563 , H01L23/481 , H01L23/49816 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555
Abstract: 서로다른두께의반도체칩들을갖는반도체장치를제공한다. 이장치는반도체칩 상에적층된하나또는다수의얇은반도체칩들을구비한다. 상기얇은반도체칩들은다수의관통전극들(TSV)을구비하며상기반도체칩보다작은두께를갖는다. 상기얇은반도체칩들중 선택된하나의표면에형성된다수의외부접속단자들이제공된다. 상기외부접속단자들은상기관통전극들(TSV)을경유하여상기반도체칩 및상기얇은반도체칩들에전기적으로접속된다.
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