公开(公告)号：KR101179386B1

公开(公告)日：2012-09-03

申请号：KR1020100032244

申请日：2010-04-08

Applicant: 삼성전기주식회사 ,  성균관대학교산학협력단

Inventor： 박승욱 ,  권영도 ,  김장현 ,  박태석 ,  서수정 ,  장재권 ,  김남정 ,  임승규 ,  이광근

IPC: H01L23/12 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01L21/50 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19015 ,  H01L2924/19041 ,  Y10T436/170769 ,  H01L2224/13099

Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.

公开(公告)号：KR1020110127513A

公开(公告)日：2011-11-25

申请号：KR1020100047043

申请日：2010-05-19

Applicant: 성균관대학교산학협력단

Inventor： 서수정 ,  임승규 ,  박화선 ,  박태석 ,  김진수 ,  나성훈 ,  이창형 ,  장재권

IPC: H01L23/488

CPC classification number: H01L2224/10

Abstract: PURPOSE: A method for manufacturing a silicon interposer is provided to easily form a solder bump by overcharging copper in the TSV(Through Silicon Via) of a substrate and projecting a copper post more than the substrate. CONSTITUTION: A TSV(Through Silicon Via)(130) is formed in a silicon substrate. An oxide film(140) and a copper seed layer(150) are formed in the silicon substrate in which the TSV is formed. A mask layer is formed in the upper side and the lower side of the silicon substrate. A copper post is formed to be dented more than a mask layer. One end of the cooper post is projected more than the silicon substrate by filling the copper in the TSV. Solder is deposited in one end of the copper post and the mask layer is removed. A solder bump is formed in one end of the copper post through a reflow process.

Abstract translation: 目的：提供一种用于制造硅插入件的方法，以便通过在基板的TSV（通过硅通孔）中对铜进行过充电而容易地形成焊料凸块，并将铜柱突出于基板以上。 构成：在硅衬底中形成TSV（硅通孔）（130）。 在形成TSV的硅衬底中形成氧化膜（140）和铜籽晶层（150）。 在硅衬底的上侧和下侧形成掩模层。 铜柱形成为比掩模层更凹陷。 通过在TSV中填充铜，铜柱的一端比硅衬底更突出。 在铜柱的一端沉积焊料，去除掩模层。 通过回流工艺在铜柱的一端形成焊料凸块。

公开(公告)号：KR1020110112974A

公开(公告)日：2011-10-14

申请号：KR1020100032244

申请日：2010-04-08

Applicant: 삼성전기주식회사 ,  성균관대학교산학협력단

Inventor： 박승욱 ,  권영도 ,  김장현 ,  박태석 ,  서수정 ,  장재권 ,  김남정 ,  임승규 ,  이광근

IPC: H01L23/12 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01L21/50 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19015 ,  H01L2924/19041 ,  Y10T436/170769 ,  H01L2224/13099

Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.

公开(公告)号：KR1020140035652A

公开(公告)日：2014-03-24

申请号：KR1020120102157

申请日：2012-09-14

Applicant: 삼성전기주식회사 ,  성균관대학교산학협력단

Inventor： 문성재 ,  김진수 ,  남효승 ,  서수정 ,  곽준호 ,  박태석 ,  류창섭

IPC: H01L21/768 ,  H05K3/40

Abstract: The present invention relates to a printed circuit board including a first conductive layer and a via part electrically connected to the first conductive layer, and the shortest distance from the via part and an interface of the first conductive layer to a bottom surface of the first conductive layer is shorter than a height of the first conductive layer.

Abstract translation: 本发明涉及一种印刷电路板，其包括第一导电层和电连接到第一导电层的通孔部分，并且与第一导电层的通孔部分和界面到第一导电层的底表面的最短距离 层比第一导电层的高度短。

公开(公告)号：KR101152267B1

公开(公告)日：2012-06-08

申请号：KR1020100047043

申请日：2010-05-19

Applicant: 성균관대학교산학협력단

Inventor： 서수정 ,  임승규 ,  박화선 ,  박태석 ,  김진수 ,  나성훈 ,  이창형 ,  장재권

IPC: H01L23/488

CPC classification number: H01L2224/10

Abstract: 본발명은기판의 TSV에구리를과충진하여구리포스트가기판보다돌출되게함으로써솔더범프의형성이용이하고, 제작공정을단축시킬수 있는실리콘인터포저의제작방법에관한것으로서, 실리콘기판을준비하는단계; 실리콘기판에 TSV(Through Silicon Via)를형성하는단계; TSV가형성된실리콘기판에산화막및 구리시드층을형성하는단계; 실리콘기판의상면과하면에마스크층을형성하는단계; TSV에구리를충진하여일단이실리콘기판보다돌출되고마스크층보다함몰된형태의구리포스트를형성하는단계; 구리포스트의일단에솔더를증착하고, 마스크층을제거하는단계; 및리플로우공정을통해구리포스트의일단에솔더범프를형성하는단계를포함한다.