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公开(公告)号：KR1020140035701A
公开(公告)日：2014-03-24
申请号：KR1020120102287
申请日：2012-09-14
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H05K3/188 , C23C18/1637 , C23C18/1651 , C23C18/1844 , C23C18/36 , C23C18/44 , C23C18/48 , C23C18/54 , H05K1/09 , H05K3/244 , H05K2201/0344 , H05K2203/073
Abstract: The present invention provides a method for forming an Au thin film, which includes the steps of: forming an Ni plating layer by the electroless Ni plating of the surface of an object; forming a Pd-Cu mixed plating layer by the electroless Pd-Cu mixture plating of the Ni plating layer; and forming a first Au thin film layer by substituting Au for Cu elements of a Pd-Cu mixture by a substitution reaction by immersing the Pd-Cu mixed plating layer in Au galvanic electrolytes. [Reference numerals] (S10) Step for removing a copper print circuit substrate oxide film; (S20) Catalyst activation step; (S30) Ni electroless plating step; (S40) Pd electroless plating step; (S50) Pd-Cu mixture electroless plating step; (S60) Gold galvanic replacement reaction step; (S70) Gold electroless plating step
Abstract translation: 本发明提供一种形成Au薄膜的方法，其包括以下步骤：通过对象表面的无电Ni镀层形成Ni镀层; 通过Ni镀层的无电Pd-Cu混合电镀形成Pd-Cu混合镀层; 以及通过将Pd-Cu混合镀层浸入Au电解电解质中，通过置换反应将Au代替为Pd-Cu混合物的Cu元素，形成第一Au薄膜层。 （附图标记）（S10）去除铜印刷电路基板氧化膜的步骤; （S20）催化剂活化步骤; （S30）镍化学镀步骤; （S40）Pd化学镀步骤; （S50）Pd-Cu混合物电镀步骤; （S60）金电镀替代反应步骤; （S70）金化学镀步骤
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公开(公告)号：KR1020140035652A
公开(公告)日：2014-03-24
申请号：KR1020120102157
申请日：2012-09-14
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
IPC: H01L21/768 , H05K3/40
Abstract: The present invention relates to a printed circuit board including a first conductive layer and a via part electrically connected to the first conductive layer, and the shortest distance from the via part and an interface of the first conductive layer to a bottom surface of the first conductive layer is shorter than a height of the first conductive layer.
Abstract translation: 本发明涉及一种印刷电路板，其包括第一导电层和电连接到第一导电层的通孔部分，并且与第一导电层的通孔部分和界面到第一导电层的底表面的最短距离 层比第一导电层的高度短。
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公开(公告)号：KR1020150146287A
公开(公告)日：2015-12-31
申请号：KR1020140076662
申请日：2014-06-23
Applicant: 삼성전기주식회사
CPC classification number: H05K3/4682 , H05K3/0097 , H05K3/4673 , H05K2201/096 , H05K2203/1536 , Y10T29/49156
Abstract: 본발명은인쇄회로기판및 인쇄회로기판의제조방법에관한것이다. 본발명의실시예에따른인쇄회로기판은절연층, 절연층의하면에형성되어절연층에매립되도록형성된제1 외층회로패턴및 절연층상면에형성되어절연층으로부터돌출되도록형성된제2 외층회로패턴을포함한다.
Abstract translation: 印刷电路板及其制造方法技术领域本发明涉及印刷电路板及其制造方法。 根据本发明的一个实施例，印刷电路板包括：绝缘层，第一外层电路图案，其形成在绝缘层的下表面上并埋在绝缘层中; 以及第二外层电路图案，其形成在绝缘层的上表面上并从绝缘层突出。
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公开(公告)号：KR1020150046615A
公开(公告)日：2015-04-30
申请号：KR1020130126060
申请日：2013-10-22
Applicant: 삼성전기주식회사
IPC: H05K3/46
CPC classification number: H05K1/185 , H05K3/429 , H05K3/4644 , H05K3/4697 , H05K2201/096 , H05K2201/09709 , H05K2201/0979
Abstract: 본발명은다층인쇄회로기판에관한것이다. 본발명에따른인쇄회로기판은코어층상부에적층형성된스택(stack) 비아; 상기스택비아양측에형성되며, 상기코어층상부에적층되는스태거드(staggered) 비아; 및코어층하부에적층되며, 상기스택비아및 스태거드비아의오픈영역외의절연층상에적층된솔더레지스트층;으로구성되어상기스태거비아에형성된다수의비아들이강성을증대시시켜기판의휨을방지하는효과가있다.
Abstract translation: 多层印刷电路板技术领域本发明涉及一种多层印刷电路板。 多层印刷电路板包括：层叠形成于芯层顶部的叠层; 形成在堆叠通孔的两侧的交错通孔，并层压到芯层的顶部; 以及层叠在芯层的底部上的阻焊层，并且除了堆叠通孔的开放区域和交错通孔之外层叠有绝缘层，其中形成在交错通孔上的多个通孔增加刚性以防止弯曲基板 。
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公开(公告)号：KR1020100064042A
公开(公告)日：2010-06-14
申请号：KR1020080122455
申请日：2008-12-04
Applicant: 삼성전기주식회사
IPC: H01L21/208 , H01L21/3205
CPC classification number: H01L21/76879 , C25D3/12 , C25D3/38 , C25D3/44 , C25D3/48 , C25D3/54 , H01L21/2885
Abstract: PURPOSE: An electrolytic plating device and a method for manufacturing a wafer penetration electrode are provided to improve electrical reliability by increasing adhesion inside a hole with a metal seed layer. CONSTITUTION: An electrolytic plating device includes a cathode auxiliary device(10) and an anode and fills a penetration hole of a wafer with conductive materials. A cathode auxiliary device includes an elastic pad, a pressure unit(16), and a metal film(13). The wafer is arranged on one side of the elastic pad. The pressure unit pressurizes the elastic pad in the direction of the wafer. The metal film is interposed between the elastic pad and the wafer, is replaceable, and is electrically connected to the anode.
Abstract translation: 目的：提供一种电解电镀装置和晶片穿透电极的制造方法，通过增加金属种子层内的孔内的附着力来提高电可靠性。 构成：电解电镀装置包括阴极辅助装置（10）和阳极，并用导电材料填充晶片的穿透孔。 阴极辅助装置包括弹性垫，压力单元（16）和金属膜（13）。 晶片布置在弹性垫的一侧。 压力单元沿着晶片的方向对弹性垫进行加压。 金属膜介于弹性垫和晶片之间，是可更换的，并且电连接到阳极。
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Patent Agency Ranking
公开(公告)号：KR1020090070107A
公开(公告)日：2009-07-01
申请号：KR1020070137995
申请日：2007-12-26
Applicant: 삼성전기주식회사
CPC classification number: B01J35/0013 , B01J27/04 , B01J27/047 , B01J35/002 , B01J37/08 , B01J37/20 , C01B3/0084 , H01M8/1011 , H01M8/1016 , H01M2300/0082 , Y02E60/324 , Y02E60/523 , Y02P70/56
Abstract: A method for manufacturing layered nanoparticles with a simple process is provided to enable various kinds of layered nanoparticles to be produced by using different sorts of metal halide precursors. A method for manufacturing layered nanoparticles comprises the following steps of: adding metal halide precursors and sulfur precursors to an amine-containing organic solvent to prepare a mixed solution; heating the mixed solution at predetermined temperature to manufacture metal sulfide nanoparticles; and separating the metal sulfide nanoparticles from the mixed solution. In the mixed solution preparation step, the metal halide precursors is selected from the group of MaXb, wherein M is metal, 1
Abstract translation: 提供了一种通过简单的方法制造层状纳米颗粒的方法，以通过使用不同种类的金属卤化物前体来制备各种分层的纳米颗粒。 制备层状纳米颗粒的方法包括以下步骤：向含胺有机溶剂中加入金属卤化物前体和硫前体以制备混合溶液; 在预定温度下加热混合溶液以制备金属硫化物纳米颗粒; 并从混合溶液中分离金属硫化物纳米颗粒。 在混合溶液制备步骤中，金属卤化物前体选自MaXb，其中M是金属，1≤a≤7，X = F，Cl，Br和I，1≤b≤9。
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公开(公告)号：KR100803004B1
公开(公告)日：2008-02-14
申请号：KR1020060097440
申请日：2006-10-02
Applicant: 삼성전기주식회사
IPC: C25D7/12
CPC classification number: C25D7/123 , H01L21/2885
Abstract: A method for filling through holes is provided to prevent inlets of the through holes from be excessively coated, perform filling of a filling material into the through holes more compactly, and enhance adhesion of the filling material with inner walls of the through holes. As a method for filling a conductor in through holes formed in a substrate, the method for filling the through holes comprises: (a) a seed layer forming step(S100) of depositing conductive metal onto portions of inner wall surfaces of the through holes to form a seed layer; (b) a plugging step(S200) of performing an electroplating operation to fill portions of the through holes with a conductor; and (c) a growing step(S300) of performing the electroplating operation to fill residual portions of the through holes with the conductor. The step(a) is carried out by depositing conductive metal onto one face of the substrate. The step(a) comprises controlling deposition thickness of the conductive metal deposited onto the one face of the substrate to control depth of the seed layer formed on the inner wall surfaces of the through holes. The step(b) is conducted by controlling a current density applied to both faces of the substrate.
Abstract translation: 提供一种用于填充通孔的方法以防止通孔的入口被过度涂覆，更紧凑地填充填充材料到通孔中，并且增强了填充材料与通孔的内壁的粘附性。 作为将导体填充到形成于基板的贯通孔的方法，填充通孔的方法包括：（a）将导电金属沉积在通孔的内壁面的部分上的种子层形成工序（S100） 形成种子层; （b）进行电镀操作以用导体填充所述通孔的部分的封堵步骤（S200）; 和（c）进行电镀操作以用导体填充通孔的剩余部分的生长步骤（S300）。 步骤（a）通过将导电金属沉积在基底的一个面上来进行。 步骤（a）包括控制沉积在基板的一个面上的导电金属的沉积厚度，以控制形成在通孔的内壁表面上的种子层的深度。 步骤（b）通过控制施加到基板的两个面的电流密度来进行。
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公开(公告)号：KR101497840B1
公开(公告)日：2015-03-02
申请号：KR1020130148573
申请日：2013-12-02
Applicant: 삼성전기주식회사
IPC: H05K3/34
CPC classification number: H05K1/111 , H05K2201/099 , H05K2201/09909 , H05K2201/2081 , Y02P70/611
Abstract: 본 발명은 솔더레지스트 개구 구조 및 회로 기판에 관한 것이다. 본 발명의 하나의 실시예에 따라, 제1 허용오차를 갖는 80㎛ 이하의 하부직경을 갖고 전극패드를 노출시키는 솔더레지스트 개구 구조에 있어서, 하부직경은 전극패드의 직경보다 작고, 하부직경보다 상부직경이 크게 형성된 단면상 역사다리꼴 형상이고, 상부직경과 하부직경의 직경차는 10㎛ 이상이고 제2 허용오차를 가지며 하부직경이 줄어들수록 증가하고, 제1 및 제2 허용오차는 2.5㎛미만인 것을 특징으로 하는 솔더레지스트 개구 구조가 제안된다. 또한, 회로 기판이 제안된다.
Abstract translation: 本发明涉及阻焊剂和电路板的开口结构。 根据本发明的一个实施例，在具有第一允许误差的底部直径为80um或更小的阻焊剂的开口结构中，露出电极焊盘，底部直径在横截面上具有相反的梯形形状。 底部直径小于电极焊盘的直径。 底部直径大于顶部直径。 顶部直径和底部直径之间的差为10um以上，具有第二容许误差，并且随着底部直径的减小而增加。 第一个允许误差和第二个允许误差低于2.5um。 建议使用阻焊剂的开口结构，并提出电路板。
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公开(公告)号：KR1020140080117A
公开(公告)日：2014-06-30
申请号：KR1020120149571
申请日：2012-12-20
Applicant: 삼성전기주식회사
CPC classification number: C23C18/163 , C23C18/1675 , H05K3/187 , H05K2203/072 , H05K2203/1518 , H05K2203/1554 , H05K2203/159
Abstract: The present invention relates to a basket jig for electroless plating. The electroless plating jig according to the present invention comprises: a basket on which multiple printed circuit boards are loaded; a rotary structure coupled to the upper part of both sides of the basket; and a tube coupled to the bottom of the basket to be injected with fluid.
Abstract translation: 本发明涉及一种用于化学镀的篮子夹具。 根据本发明的化学镀敷夹具包括：一个其上装有多个印刷电路板的筐; 旋转结构，其联接到所述篮的两侧的上部; 以及耦合到篮子底部以被注入流体的管。
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公开(公告)号：KR1020140047890A
公开(公告)日：2014-04-23
申请号：KR1020120114185
申请日：2012-10-15
Applicant: 삼성전기주식회사
Abstract: The present invention relates to a method to enhance adhesion of a surface of a low profile substrate comprising a step of hydrophilic treating a substrate surface; and a step of chemical copper plating the hydrophilic treated substrate. According to an embodiment of the present invention, in order to implement a fine circuit pattern on the low profile substrate, blister generation is suppressed through surface hydrophilic treatment using air pressure plasma and a chemical copper plating process so that formation of a fine circuit pattern is possible and the adhesion effect with the formed fine circuit pattern is improved. [Reference numerals] (AA) Surface hydrophilic treatment step; (BB) Organic matter removing step on a base surface; (CC) Surface activation step; (DD) Catalyst adsorption step; (EE) Catalyzed step; (FF) Chemical copper plating step; (GG) Dry film (DF) processing step; (HH) Pattern forming step
Abstract translation: 本发明涉及一种增强低轮廓基材表面粘合性的方法，包括亲水处理基材表面的步骤; 以及对亲水处理的基材进行化学镀铜的步骤。 根据本发明的一个实施例，为了在薄型基板上实现精细电路图案，通过使用空气压力等离子体和化学镀铜处理的表面亲水处理来抑制泡罩的产生，从而形成精细电路图案是 提高了形成的精细电路图案的可能性和附着效果。 （AA）表面亲水处理工序; （BB）基面上的有机物去除步骤; （CC）表面活化步骤; （DD）催化剂吸附步骤; （EE）催化步骤; （FF）化学镀铜步骤; （GG）干膜（DF）加工步骤; （HH）图案形成步骤
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