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公开(公告)号：KR101044973B1
公开(公告)日：2011-06-29
申请号：KR1020090053852
申请日：2009-06-17
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 고저항체로 사용할 수 있는 고저항 서멧 저항체 및 그 형성방법에 관한 것이다.
본 발명에 의한 고저항 서멧 저항체의 형성방법은, 고저항체로 사용되는 서멧 저항체를 형성하는 방법에 있어서, 양극산화가 쉽게 이루어지는 활성물질과 양극산화에 안정한 안정금속을 함께 증착하여 혼합체를 형성하고, 상기 혼합체를 양극산화하여 상기 활성물질만 선택적으로 산화된 서멧을 형성하는 것을 특징으로 한다. 또한 본 발명에 의한 고저항 서멧 저항체는 양극산화가 쉽게 이루어지는 활성물질을 양극산화한 산화물을 기반으로 하여 양극산화에 안정한 안정금속 입자가 분산된 상태의 서멧으로 이루어진 것을 특징으로 한다.
본 발명에 따르면, 증착공정을 실시한 뒤에 양극산화공정을 실시하여 산소결핍의 문제를 방지함으로써, 뛰어난 열안정성 및 고주파특성을 갖는 고저항체를 제조할 수 있으며, 서멧을 직접 증착하지 않기 때문에 증착과정에서 옥사이드 타겟 또는 산소기체를 사용하지 않음으로써, 증착용 챔버의 오염을 막을 수 있는 효과가 있다.
양극산화, 애노다이징, 서멧, cermet, 저항-
公开(公告)号：KR1020100135469A
公开(公告)日：2010-12-27
申请号：KR1020090053852
申请日：2009-06-17
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A high resistance cermet resistor and a forming method thereof are provided to prevent hypoxia by selectively performing anodizing process after a deposition process. CONSTITUTION: A first photoresist pattern is formed on a substrate(10). A metal electrode(30) is deposited on the front of a substrate. A first photo resistor pattern is removed from the substrate. A second photo resist pattern is formed on the substrate without a resistor formation position. A mixture is deposited on the front of the substrate and is made of active material and stable metal. A cermet resistor(60) is formed by anodizing the mixture. A second photoresist pattern is removed from the substrate.
Abstract translation: 目的：提供高电阻金属陶瓷电阻器及其形成方法，以在沉积工艺之后选择性地进行阳极氧化处理来防止缺氧。 构成：在衬底（10）上形成第一光致抗蚀剂图案。 金属电极（30）沉积在基板的前面。 从衬底去除第一光电阻图案。 在基板上形成第二光刻胶图案，而不形成电阻器形成位置。 混合物沉积在基材的前面，并由活性材料和稳定的金属制成。 通过阳极氧化混合物形成金属陶瓷电阻（60）。 从衬底去除第二光致抗蚀剂图案。
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Patent Agency Ranking
公开(公告)号：KR101179386B1
公开(公告)日：2012-09-03
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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公开(公告)号：KR1020110129092A
公开(公告)日：2011-12-01
申请号：KR1020100048526
申请日：2010-05-25
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A manufacturing method of a passive component embedded substrate is provided to manufacture an electronic product of an excellent structure with high reliability, thereby extending a lifespan of the electronic product and making a slimmer finished product. CONSTITUTION: A penetration hole(20) for embedding a passive component is arranged in a substrate. A via hole(10) for wiring is arranged in the substrate. The via hole for wiring is plated. A support stand is attached in one surface of the substrate. The passive component is embedded through the penetration hole. The wiring is arranged by plating the penetration hole for embedding the passive component.
Abstract translation: 目的：提供一种无源部件嵌入式基板的制造方法，以制造具有高可靠性的优异结构的电子产品，从而延长电子产品的寿命并制成更细的成品。 构成：用于嵌入无源部件的贯通孔（20）布置在基板中。 用于布线的通孔（10）设置在基板中。 接线用通孔进行电镀。 在基板的一个表面上附着支撑台。 被动部件通过穿透孔嵌入。 布线通过电镀用于嵌入被动元件的穿透孔而布置。
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公开(公告)号：KR1020110127513A
公开(公告)日：2011-11-25
申请号：KR1020100047043
申请日：2010-05-19
Applicant: 성균관대학교산학협력단
IPC: H01L23/488
CPC classification number: H01L2224/10
Abstract: PURPOSE: A method for manufacturing a silicon interposer is provided to easily form a solder bump by overcharging copper in the TSV(Through Silicon Via) of a substrate and projecting a copper post more than the substrate. CONSTITUTION: A TSV(Through Silicon Via)(130) is formed in a silicon substrate. An oxide film(140) and a copper seed layer(150) are formed in the silicon substrate in which the TSV is formed. A mask layer is formed in the upper side and the lower side of the silicon substrate. A copper post is formed to be dented more than a mask layer. One end of the cooper post is projected more than the silicon substrate by filling the copper in the TSV. Solder is deposited in one end of the copper post and the mask layer is removed. A solder bump is formed in one end of the copper post through a reflow process.
Abstract translation: 目的：提供一种用于制造硅插入件的方法，以便通过在基板的TSV（通过硅通孔）中对铜进行过充电而容易地形成焊料凸块，并将铜柱突出于基板以上。 构成：在硅衬底中形成TSV（硅通孔）（130）。 在形成TSV的硅衬底中形成氧化膜（140）和铜籽晶层（150）。 在硅衬底的上侧和下侧形成掩模层。 铜柱形成为比掩模层更凹陷。 通过在TSV中填充铜，铜柱的一端比硅衬底更突出。 在铜柱的一端沉积焊料，去除掩模层。 通过回流工艺在铜柱的一端形成焊料凸块。
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公开(公告)号：KR1020110112974A
公开(公告)日：2011-10-14
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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公开(公告)号：KR101152267B1
公开(公告)日：2012-06-08
申请号：KR1020100047043
申请日：2010-05-19
Applicant: 성균관대학교산학협력단
IPC: H01L23/488
CPC classification number: H01L2224/10
Abstract: 본발명은기판의 TSV에구리를과충진하여구리포스트가기판보다돌출되게함으로써솔더범프의형성이용이하고, 제작공정을단축시킬수 있는실리콘인터포저의제작방법에관한것으로서, 실리콘기판을준비하는단계; 실리콘기판에 TSV(Through Silicon Via)를형성하는단계; TSV가형성된실리콘기판에산화막및 구리시드층을형성하는단계; 실리콘기판의상면과하면에마스크층을형성하는단계; TSV에구리를충진하여일단이실리콘기판보다돌출되고마스크층보다함몰된형태의구리포스트를형성하는단계; 구리포스트의일단에솔더를증착하고, 마스크층을제거하는단계; 및리플로우공정을통해구리포스트의일단에솔더범프를형성하는단계를포함한다.
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