Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor structure and electronic device, formed in high density, and having smaller structural dimensions and a more exact shape.SOLUTION: Semiconductor structures and electronic devices include at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material.
Abstract:
A method for fabricating a photovoltaic device includes applying (206) a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited (212) on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off (214) and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched (216) using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
Abstract:
Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.
Abstract:
Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.
Abstract:
Es ist ein Streifen aus Graphen mit einer Breite von weniger als 3 nm, bevorzugter mit einer Breite von weniger als 1 nm offenbart. In einer bevorzugteren Ausführungsform sind mehrere Streifen aus Graphen vorhanden, wobei jeder eine Breite mit einer der folgenden Abmessungen aufweist: die Länge von zwei Phenylringen, die zusammengeschmolzen sind, die Länge von drei Phenylringen, die zusammengeschmolzen sind, die Länge von vier Phenylringen, die zusammengeschmolzen sind, und die Länge von fünf Phenylringen, die zusammengeschmolzen sind. In einer weiteren bevorzugten Ausführungsform sind die Kanten der Streifen parallel zueinander. In einer weiteren bevorzugten Ausführungsform weisen die Streifen wenigstens eine Sesselkante auf und können größere Breiten aufweisen. Die Erfindung weist des Weiteren ein Verfahren zum Herstellen eines Streifens aus Graphen auf, das die Schritte aufweist: a. Anordnen von einer oder mehreren polyaromatischen Kohlenwasserstoff(PAH)-Vorläuferverbindungen auf einem Substrat; b. Anwenden von UV-Licht auf den PAH, bis eine oder mehrere intermolekulare Bindungen zwischen benachbarten PAH-Molekülen gebildet sind; und
Abstract:
A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
Abstract:
Disclosed is a ribbon of graphene less than 3 run wide, more preferably less than 1 nm wide. In a more preferred embodiment, there are multiple ribbons of graphene each with a width of one of the following dimensions: the length of 2 phenyl rings fused together, the length of 3 phenyl rings fused together, the length of 4 phenyl rings fused together, and the length of 5 phenyl rings fused together. In another preferred embodiment the edges of the ribbons are parallel to each other. In another preferred embodiment, the ribbons have at least one arm chair edge and may have wider widths.
Abstract:
A silicon nitride layer 16 is provided on an uppermost surface of a graphene layer 14 and then a hafnium dioxide layer 18 is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. The graphene layer can be epitaxially grown on a substrate which may be silicon carbide. The silicon nitride layer may be a tensile silicon nitride layer. A portion of the graphene layer may serve as a channel layer for a FET. The graphene layer may be in contact with source and drain regions of an FET 56, 58. A gate conductor 54 may be located on the hafnium oxide layer. The dielectric bilayer may cover the sides and the top of the source drain regions.