公开(公告)号：WO03009380A3

公开(公告)日：2003-08-07

申请号：PCT/GB0201370

申请日：2002-03-21

Applicant: IBM ,  IBM UK

Inventor： CONTI RICHARD ,  DEV PRAKASH ,  DOBUZINSKY DAVID MARK ,  EDELSTEIN DANIEL CHARLES ,  LEE GILL ,  LOW KIA-SENG ,  SHAFER PADRAIC ,  SIMPSON ALEXANDER ,  WRSCHKA PETER

IPC: H01L21/28 ,  H01L21/316 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract translation: 公开了一种用于在衬底上方具有碳渐变层的绝缘体层的结构和方法，其中在衬底上方的每个连续碳渐变层中的碳浓度增加。 绝缘体包括具有小于3.3的介电常数的低k电介质。 碳渐变层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘附力。 该结构还可以包括碳梯度层之间的稳定界面。 更具体地说，碳缓变层包括与碳含量在约5％和20％之间的衬底相邻的第一层，在第一层之上的含碳量在约10％和30％之间的第二层，以及第三层 在碳含量在约20％和40％之间的第二层之上。

公开(公告)号：AU2002241147A1

公开(公告)日：2003-03-03

申请号：AU2002241147

申请日：2002-03-21

Applicant: IBM

Inventor： DEV PRAKASH ,  EDELSTEIN DANIEL CHARLES ,  SHAFER PADRAIC ,  SIMPSON ALEXANDER ,  LOW KIA-SENG ,  WRSCHKA PETER ,  CONTI RICHARD ,  DOBUZINSKY DAVID MARK ,  LEE GILL

IPC: H01L21/28 ,  H01L21/316 ,  H01L23/532 ,  H01L29/51

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

公开(公告)号：DE10226569A1

公开(公告)日：2003-01-16

申请号：DE10226569

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  DEV PRAKASH ,  MALIK RAJEEV ,  NESBIT LARRY

IPC: H01L21/8242 ,  H01L27/108

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.