公开(公告)号：EP2020031A4

公开(公告)日：2011-11-02

申请号：EP07761242

申请日：2007-04-25

Applicant: IBM

Inventor： DYER THOMAS W ,  YANG HAINING S

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/01 ,  H01L27/092 ,  H01L29/00 ,  H01L29/04 ,  H01L29/78 ,  H01L31/036

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：JP2007329474A

公开(公告)日：2007-12-20

申请号：JP2007135089

申请日：2007-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  FANG SUNFEI ,  HOLT JUDSON R

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/7853

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate having different surface orientations (namely, hybrid surface orientation).
SOLUTION: In the semiconductor substrate, a first device area 2 has a substantially flat surface 16A which is oriented to one orientation of group of first equivalent crystal surfaces, and a second device area contains a protrusive semiconductor structure 18 having a plurality of cross surfaces 16B which are oriented to an orientation of group of other equivalent crystal surfaces. A semiconductor device structure can be formed using such a semiconductor substrate. Particularly, a first field-effect transistor (FET) can be formed in the first device area, the first FET contains a channel which is located along a substantially flat surface in the first device area. A second complementary FET can be formed in the second device area, and the second complementary FET contains a channel which is located along the plurality of cross surfaces of the protrusive semiconductor structure in the second device area.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有不同表面取向（即混合表面取向）的半导体衬底。 解决方案：在半导体衬底中，第一器件区域2具有基本上平坦的表面16A，其被定向为第一等效晶体表面的一组取向，并且第二器件区域包含突出半导体结构18，突出半导体结构18具有多个 横向表面16B被定向成其他等效晶体表面的组的取向。 可以使用这种半导体衬底形成半导体器件结构。 特别地，第一场效应晶体管（FET）可以形成在第一器件区域中，第一FET包含沿着第一器件区域中的基本上平坦的表面定位的沟道。 第二互补FET可以形成在第二器件区域中，并且第二互补FET包含沿着第二器件区域中的突出半导体结构的多个十字表面定位的沟道。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007251163A

公开(公告)日：2007-09-27

申请号：JP2007057115

申请日：2007-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  YANG HAINING ,  LUO ZHIJIONG

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor-on-insulator (SOI) substrate which has a patterned buried insulator layer included in differing depths. SOLUTION: The SOI substrate has a substantially planar upper surface and further includes: (1) first regions that include no buried insulator in any way; (2) second regions that include first portions of a patterned buried insulator layer 12 at a first depth (i.e., a depth measured from the planar upper surface of the SOI substrate); and (3) third regions that include second portions of the patterned buried insulator layer 12 at a second depth, wherein the first depth is deeper than the second depth. One or more field effect transistors (FETs) 20, 40 can be formed in the SOI substrate. For example, the FETs may have: channel regions in the first regions of the SOI substrate; source regions and drain regions in the second regions of the SOI substrate; and source/drain extension regions in the third regions of the SOI substrate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有不同深度的图案化掩埋绝缘体层的绝缘体上半导体（SOI）衬底。 解决方案：SOI衬底具有基本平坦的上表面，并且还包括：（1）以任何方式不包括埋入绝缘体的第一区域; （2）在第一深度（即从SOI衬底的平面上表面测量的深度）上包括图案化的掩埋绝缘体层12的第一部分的第二区域; 和（3）第三区域，其包括在第二深度处的图案化掩埋绝缘体层12的第二部分，其中第一深度比第二深度深。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）20,40。 例如，FET可以在SOI衬底的第一区域中具有：沟道区域; SOI衬底的第二区域中的源极区和漏极区; 以及SOI衬底的第三区域中的源极/漏极延伸区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO0229888A3

公开(公告)日：2002-08-29

申请号：PCT/US0127366

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KNORR ANDREAS ,  ECONOMIKOS LAERTIS ,  HALLE SCOTT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10891

Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride (16) remaining in place. Once the devices have been formed and the gate polysilicon (18) has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide (21) fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成具有衬垫氮化物（16）保持就位的垂直器件而形成。 一旦器件已经形成并且栅极多晶硅（18）已被平坦化到衬垫氮化物的表面，衬垫氮化物被剥离，留下栅极多晶硅插塞的顶部延伸到有源硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物（21）填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO2007127769A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067360

申请日：2007-04-25

Applicant: IBM ,  DYER THOMAS W ,  YANG HAINING S

Inventor： DYER THOMAS W ,  YANG HAINING S

IPC: H01L21/8232 ,  H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

Abstract translation: 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

公开(公告)号：WO02086904A2

公开(公告)日：2002-10-31

申请号：PCT/US0210892

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN P ,  JAIPRAKASH VENKATACHAIAM C ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract translation: 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间​​的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间​​的短路。

公开(公告)号：DE10296608T5

公开(公告)日：2004-04-22

申请号：DE10296608

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN ,  PRAKASH V C JAI ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

公开(公告)号：DE10296608B4

公开(公告)日：2010-10-14

申请号：DE10296608

申请日：2002-04-08

Applicant: IBM ,  QIMONDA AG

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN ,  PRAKASH JAI V C ,  RADENS CARL

IPC: H01L21/8242 ,  H01L27/108