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    CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES
    1.
    发明申请
    CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES 审中-公开
    用于改善低介电常数硅基底粘附的碳分层

    公开(公告)号：WO03009380A3

    公开(公告)日：2003-08-07

    申请号：PCT/GB0201370

    申请日：2002-03-21

    Applicant: IBM ,  IBM UK

    Inventor： CONTI RICHARD ,  DEV PRAKASH ,  DOBUZINSKY DAVID MARK ,  EDELSTEIN DANIEL CHARLES ,  LEE GILL ,  LOW KIA-SENG ,  SHAFER PADRAIC ,  SIMPSON ALEXANDER ,  WRSCHKA PETER

    IPC: H01L21/28 ,  H01L21/316 ,  H01L23/532 ,  H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

    Abstract translation: 公开了一种用于在衬底上方具有碳渐变层的绝缘体层的结构和方法，其中在衬底上方的每个连续碳渐变层中的碳浓度增加。 绝缘体包括具有小于3.3的介电常数的低k电介质。 碳渐变层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘附力。 该结构还可以包括碳梯度层之间的稳定界面。 更具体地说，碳缓变层包括与碳含量在约5％和20％之间的衬底相邻的第一层，在第一层之上的含碳量在约10％和30％之间的第二层，以及第三层 在碳含量在约20％和40％之间的第二层之上。

    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY
    2.
    发明申请
    SPACER INTEGRATION SCHEME IN MRAM TECHNOLOGY 审中-公开
    MRAM技术中的间隔整合方案

    公开(公告)号：WO2004032144A3

    公开(公告)日：2004-08-05

    申请号：PCT/EP0310678

    申请日：2003-09-24

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： COSTRINI GREG ,  HUMMEL JOHN P ,  LOW KIA-SENG ,  FINDEIS FRANK ,  KASKO IGOR ,  RABERG WOLFGANG

    IPC: G11B5/127 ,  G11B5/33 ,  G11C11/00 ,  G11C11/15 ,  G11C11/34 ,  H01L21/00 ,  H01L21/331 ,  H01L21/335 ,  H01L21/8232 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22 ,  H01L31/0352 ,  H01L43/12

    CPC classification number: H01L43/12

    Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

    Abstract translation: 通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。 通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。 在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。 在间隔物形成之后，进行第二次蚀刻以隔离该装置。 器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

    PATTERNING METAL STACK LAYERS OF MAGNETIC SWITCHING DEVICE, UTILIZING A BILAYER METAL HARDMASK
    3.
    发明申请
    PATTERNING METAL STACK LAYERS OF MAGNETIC SWITCHING DEVICE, UTILIZING A BILAYER METAL HARDMASK 审中-公开
    磁性切换装置的金属堆叠层，利用双层金属硬质合金

    公开(公告)号：WO2004040602A2

    公开(公告)日：2004-05-13

    申请号：PCT/EP0312017

    申请日：2003-10-29

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： COSTRINI GREG ,  HUMMEL JOHN P ,  STOJAKOVIC GEORGE ,  LOW KIA-SENG

    IPC: G11C11/16 ,  H01F41/30 ,  H01L43/12 ,  H01F41/00

    CPC classification number: G11C11/16 ,  B82Y25/00 ,  B82Y40/00 ,  H01F41/308 ,  H01L43/12

    Abstract: The invention relates to magnetic switching devices, and more particularly to a method for patterning metal stack layers of a magnetic switching device utilizing TiN and W as a bilayer metal hardmask (7, 8) patterned in two lithography steps with concommitant hardmask open etch and resist strip steps. The hardmask materials TiN and W are chosen so that the mask open etch chemistry is designed with good selectivity, thereby enabling patterning of the hardmask layers prior to etching of the metal stack layers.

    Abstract translation: 本发明涉及磁性开关器件，更具体地说，涉及一种利用TiN和W作为双层金属硬掩模（7,8）图案化的磁性开关器件的金属堆叠层的方法，该双层金属硬掩模（7,8）在两个光刻步骤中图案化，并具有硬掩模开放蚀刻和抗蚀剂 剥离步骤。 选择硬掩模材料TiN和W，使得掩模开口蚀刻化学品被设计成具有良好的选择性，从而能够在刻蚀金属叠层之前对硬掩模层进行图案化。

    4.
    发明专利
    未知

    公开(公告)号：DE60311131T2

    公开(公告)日：2007-10-18

    申请号：DE60311131

    申请日：2003-11-05

    Applicant: QIMONDA AG ,  IBM

    Inventor： COSTRINI GREG ,  HUMMEL P ,  KRISHNAN MAHADEVAIYER ,  LOW KIA-SENG

    IPC: G11C11/16 ,  H01F10/26 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/12

    Abstract: A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.

    7.
    发明专利
    未知

    公开(公告)号：DE60311131D1

    公开(公告)日：2007-02-22

    申请号：DE60311131

    申请日：2003-11-05

    Applicant: QIMONDA AG ,  IBM

    Inventor： COSTRINI GREG ,  HUMMEL P ,  KRISHNAN MAHADEVAIYER ,  LOW KIA-SENG

    IPC: G11C11/16 ,  H01F10/26 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/12

    Abstract: A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.

    9.
    发明专利
    未知

    公开(公告)号：DE102005034667A1

    公开(公告)日：2006-03-23

    申请号：DE102005034667

    申请日：2005-07-25

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： HUMMEL JOHN P ,  KASKO IHAR ,  LOW KIA-SENG

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/22

    Abstract: The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.

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