公开(公告)号：EP1841558A4

公开(公告)日：2012-04-04

申请号：EP05852628

申请日：2005-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER ENAMUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00 ,  B23H5/08

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

公开(公告)号：JPS62106632A

公开(公告)日：1987-05-18

申请号：JP21990286

申请日：1986-09-19

Applicant: IBM

Inventor： CLODGO DONNA J ,  PREVITI-KELLY ROSEMARY A ,  WALTON ERICK G

IPC: B32B27/00 ,  C08G77/38 ,  C08J5/18 ,  C09D183/04 ,  H01L21/312

公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：CA1223089A

公开(公告)日：1987-06-16

申请号：CA495660

申请日：1985-11-19

Applicant: IBM

Inventor： CLODGO DONNA J ,  PREVITI-KELLY ROSEMARY A ,  WALTON ERICK G

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H05K3/14 ,  H01L21/28

Abstract: A lift-off metal deposition process in which a high temperature polyimide layer (i.e. a polyimide having a high imidization temperature) is applied to a first polyimide layer. The two layers are anisotropically etched through a photoresist mask to form vias in the first polyimide layer. After application of a metal layer, the high-temperature polyimide layer is lifted off the first polyimide layer, which remains as a passivation layer.

公开(公告)号：CA2084685C

公开(公告)日：1996-01-16

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/488 ,  H01L23/50

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA2084685A1

公开(公告)日：1991-12-20

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.