公开(公告)号：US6360938B2

公开(公告)日：2002-03-26

申请号：US79459701

申请日：2001-02-27

Applicant: IBM

Inventor： DELAURENTIS STEPHEN A ,  INTERRANTE MARIO J ,  JACKSON RAYMOND A ,  KNICKERBOCKER JOHN U ,  RAY SUDIPTA K ,  STALTER KATHLEEN A

IPC: B23K1/018 ,  H01L21/687 ,  B23K31/02

CPC classification number: H01L21/687 ,  B23K1/018

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

Abstract translation: 一种用于通过在将模块加热到足以导致的温度的温度下向一个或多个倒装芯片的背面施加张力而将一个或多个去除构件施加拉力而移除通过安装在多芯片模块上的C4接头的倒装芯片的方法和装置 C4接头变得熔化。 张力可以是压缩弹簧，也可以是在室温下为平坦的双金属构件，在加热到这样的温度时变得弯曲，或者是原始形状弯曲并在室温下弯曲平坦但是返回的记忆合金 在加热到这样的温度时变成原来的弯曲形状。 使用粘合剂将去除构件粘合到要去除的芯片上，并且是固化后具有耐高温性的低温快速固化粘合剂。

公开(公告)号：CA2084685C

公开(公告)日：1996-01-16

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/488 ,  H01L23/50

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：CA2084685A1

公开(公告)日：1991-12-20

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.