公开(公告)号：DE69527761T2

公开(公告)日：2003-04-03

申请号：DE69527761

申请日：1995-11-02

Applicant: SIEMENS AG ,  IBM

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

公开(公告)号：AT222402T

公开(公告)日：2002-08-15

申请号：AT95480162

申请日：1995-11-02

Applicant: IBM ,  SIEMENS AG

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH ALBERT JOHN JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

公开(公告)号：MY134716A

公开(公告)日：2007-12-31

申请号：MYPI9300721

申请日：1993-04-21

Applicant: IBM

Inventor： BRADY MICHAEL JOHN ,  RIELEY SHELDON COLE ,  WALKER GEORGE FREDERICK ,  FARRELL CURTIS EDWARD ,  KANG SUNG KWON ,  MARINO JEFFREY ROBERT ,  MIKALSEN DONALD JOSEPH ,  MOSKOWITZ PAUL ANDREW ,  O'SULLIVAN EUGENE JOHN ,  O'TOOLE TERRENCE ROBERT ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/60 ,  H01L23/485 ,  C23C18/50 ,  C25D3/54 ,  H01L21/288 ,  H01L21/603 ,  H01L21/768 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

Abstract: SILICON AND GERANIUM CONTAINING MATERIALS ARE USED AT SURFACE OF CONDUCTORS IN ELECTRONIC DEVICES. SOLDER CAN BE FLUXLESSLY BONDED AND WIRES CAN BE WIRED BONDED TO THESE SURFACES. THESE MATERIAL ARE USED AS A SURFACE COATING FOR LEAD FRAMES FOR PACKAGING INTEGRATED CIRCUIT CHIPS. THESE MATERIALS CAN BE DECAL TRANSFERRED ONTO CONDUCTOR SURFACES OR ELECTROLESSLY OR ELECTROLYTICALLY DISPOSED THEREON.(FIG. 1)

公开(公告)号：DE69527761D1

公开(公告)日：2002-09-19

申请号：DE69527761

申请日：1995-11-02

Applicant: SIEMENS AG ,  IBM

Inventor： CONRU HAROLD WARD ,  FROEBEL FRANCIS EUGENE ,  GREGORITSCH JR ,  RIELEY SHELDON COLE ,  STARR STEPHEN GEORGE ,  UTTRECHT RONALD ROBERT ,  WHITE ERIC JEFFREY ,  POHL JENS GUENTER

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/495

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.