公开(公告)号：JP2001274343A

公开(公告)日：2001-10-05

申请号：JP2001048615

申请日：2001-02-23

Applicant: IBM

Inventor： GAUTHIER JR ROBERT J ,  SCHEPIS DOMINIC J ,  TONTI WILLIAM R ,  VOLDMAN STEVEN H

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L23/367 ,  H01L27/00 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure wherein the thermal conductivity is enhanced, and its manufacturing method. SOLUTION: During manufacturing of selected electronic components, silicon is formed at selected position on a substrate. Dielectric isolation regions are formed in an upper silicon layer and filled with a thermal conductive material. Before depositing the thermal conductive material, a liner material may be deposited at option. In a second embodiment, a horizontal layer of the thermal conductive material is deposited in an oxide layer or bulk silicon layer beneath the upper silicon layer.

公开(公告)号：JP2000101084A

公开(公告)日：2000-04-07

申请号：JP26349399

申请日：1999-09-17

Applicant: IBM

Inventor： BROWN JEFFREY S ,  GAUTHIER JR ROBERT J ,  VOLDMAN STEVEN H

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure, especially of FET, in which threshold voltage can be increased in the vicinity of corner of isolating region and a fabrication method thereof. SOLUTION: A field effect transistor has source and drain regions 26, 28, a channel region 24 between them, an isolating region 22 in a substrate, and a gate 30 including gate dopant on the channel region. The isolating region provides the corner region of channel along the interface between the channel region and the isolating region. The gate includes a region where the gate dopant is substantially depleted at least in a region where the channel region and the isolating region overlap and the threshold voltage in the channel corner region beneath the depletion region 34 increases as compared with the channel region between corner regions. A field effect transistor having an MOSFET gate 'corner part' of decreased dopant concentration improves the breakdown strength at the edge.

公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001298171A

公开(公告)日：2001-10-26

申请号：JP2001075111

申请日：2001-03-15

Applicant: IBM

Inventor： GAUTHIER JR ROBERT J ,  SCHEPIS DOMINIC J ,  STEPHEN H WOHLDMAN

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit provided with an insulator for diffusing heat from a high output device while using high-K insulating materials and for dealing with the needs of a low dielectric constant and a low resistivity for a low output logic device while using low-K insulating materials at the same time. SOLUTION: The method and the structure for forming an integrated circuit wafer are provided with a step for forming a substrate 10 having first and second parts, a step for sticking a first insulator 11 on the substrate, a step for patterning the first insulator so that the first insulator can remain only on the first part, a step for sticking a second insulator 12 on the substrate (the first insulator has heat diffusing characteristics different from the second insulator, a step for forming a planar surface by polishing the second insulator, and a step for sticking a silicon film 13 on the first insulator and the second insulator.

公开(公告)号：GB2483612A

公开(公告)日：2012-03-14

申请号：GB201200546

申请日：2010-06-17

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  GAUTHIER JR ROBERT J ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK ,  LI JUNJUN

IPC: H01L21/82 ,  H01L27/02

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

公开(公告)号：GB2505853A

公开(公告)日：2014-03-12

申请号：GB201400368

申请日：2012-06-01

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM ERIK M ,  GAUTHIER JR ROBERT J ,  GEBRESELASIE EPHREM G ,  PHELPS RICHARD A ,  SHI YUN ,  STRICKER ANDREAS D

IPC: H01L29/66 ,  H01L27/02

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include an SCR (62) with an anode (63), a cathode (65), a first region (14), and a second region (16) of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer (26) is positioned on a top surface of a semiconductor substrate (30) relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

公开(公告)号：GB2505775A

公开(公告)日：2014-03-12

申请号：GB201314519

申请日：2012-01-20

Applicant: IBM

Inventor： ABOU-KHALIL MICHAEL J ,  GAUTHIER JR ROBERT J ,  LEE TOM C ,  LI JUNJUN ,  SOUVICK MITRA ,  PUTNAM CHRISTOPHER S

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/861

Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode (56). The device structure includes one or more dielectric regions (20a, 20b, 20c), such as STI regions, positioned in the device region (18) and intersecting the p-n junction (52, 54) between an anode (40, 42) and cathode (28, 30, 48a, 48b, 49a, 49b, 50a, 50b). The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

公开(公告)号：GB2483612B

公开(公告)日：2013-07-10

申请号：GB201200546

申请日：2010-06-17

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  GAUTHIER JR ROBERT J ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK ,  LI JUNJUN

IPC: H01L21/82 ,  H01L27/02

Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

公开(公告)号：GB2497704A

公开(公告)日：2013-06-19

申请号：GB201306287

申请日：2011-09-14

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  GAUTHIER JR ROBERT J ,  LEE TOM C ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER S

IPC: H01L27/02

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

公开(公告)号：GB2509468B

公开(公告)日：2014-09-10

申请号：GB201407431

申请日：2012-08-14

Applicant: IBM

Inventor： CAMPI JOHN B ,  GAUTHIER JR ROBERT J ,  LI JUNJUN ,  MISHRA RAHUL

IPC: H01L29/74

Abstract: A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.