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    Elektronische Baugruppe für Millimeterwellen-Halbleiterplättchen
    3.
    发明专利
    Elektronische Baugruppe für Millimeterwellen-Halbleiterplättchen 未知

    公开(公告)号：DE112013001709T5

    公开(公告)日：2014-12-11

    申请号：DE112013001709

    申请日：2013-03-27

    Applicant: IBM

    Inventor： KAMINSKI NOAM ,  SHUMAKER EVGENY ,  ELAD DANNY ,  OKAMOTO KEISHI ,  TORIYAMA KAZUSHIGE

    IPC: H01L23/12 ,  H01P5/107

    Abstract: Eine mm-Wellen-Elektronikbaugruppe, welche aus einer herkömmlichen Leiterplatten(PCB)-Technologie und einer Metallabdeckung aufgebaut ist. Bei der Montage der Baugruppe wird eine Standard-Bestückungs-Technologie angewendet und Wärme wird direkt zu einem Kontaktfleck auf der Baugruppe abgeleitet. Die Eingabe/Ausgabe von mm-Wellen-Signalen) erfolgt durch einen rechteckigen Wellenleiter. Die Montage der elektronischen Baugruppe auf einer elektrischen Leiterplatte (PCB) wird unter Anwendung herkömmlicher Wiederaufschmelz-Lötverfahren durchgeführt und umfasst eine Wellenleiter-Eingabe/Ausgabe-Einheit, die mit einer mm-Wellen-Antenne verbunden ist. Die elektronische Baugruppe sorgt für eine Übertragung von Niederfrequenz-, Gleichstrom- und Massesignalen von dem Halbleiterchip innerhalb der Baugruppe zu der PCB, auf welcher er montiert ist. Durch ein Impedanzanpassungsschema wird der Übergang vom Chip zur Hochfrequenz-Leiterplatte angepasst, indem die Masseebene innerhalb des Chips verändert wird. Eine Masseebene auf der Hochfrequenz-Leiterplatte umgibt kreisförmig den Hochfrequenzsignal-Höcker, um die elektromagnetischen Felder auf die Höckerregion zu begrenzen, wodurch Strahlungsverluste verringert werden.

    Design of spacer resin pattern useful for reduction of connection loss of light between light emitting element or light receiving element and optical waveguide on semiconductor
    4.
    发明专利
    Design of spacer resin pattern useful for reduction of connection loss of light between light emitting element or light receiving element and optical waveguide on semiconductor 有权
    用于减少发光元件或光接收元件之间的光连接损失的半球形树脂图案的设计

    公开(公告)号：JP2013222075A

    公开(公告)日：2013-10-28

    申请号：JP2012093713

    申请日：2012-04-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： TOKUNARI MASAO ,  NAKANO DAIKI ,  TSUKADA YUTAKA ,  TORIYAMA KAZUSHIGE

    IPC: G02B6/122

    CPC classification number: G02B6/4236 ,  G02B6/4214 ,  H01L25/167 ,  H01L31/0232 ,  H01L33/58 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To form a spacer resin (SR) pattern layer for accurate alignment of a light emitting element or a light receiving element with both of an optical waveguide (WG) pattern layer and an electric circuit (EC) pattern layer, from a wafer level of a semiconductor.SOLUTION: A base layer which has a through hole (via) provided to electrically communicate with an electric circuit (EC) pattern layer and is made of a resin is formed on a semiconductor (GaAs) wafer. A truncated cone or polygonal pyramid-shaped three-dimensional reflecting surface is formed to guide output of emitted light to or input of received light from an optical waveguide (WG) pattern layer. A metal film being doughnut-shaped, circular, or polygonal in plan view is vapor-deposited in a prescribed range from a center positioned on the basis of the position of the through hole. A cone or pyramid-shaped mold is stamped to the center. The direction of light is corrected by a formed taper structure to increase tolerance for accuracy and to reduce light loss.

    Abstract translation: 要解决的问题：为了形成用于将光发射元件或光接收元件与光波导（WG）图案层和电路（EC）图案层两者精确对准的间隔树脂（SR）图案层，从 晶片级半导体。解决方案：在半导体（GaAs）晶片上形成具有设置用于与电路（EC）图案层电连通并由树脂制成的通孔（通孔））的基底层。 形成截锥体或多角锥形的三维反射表面以将发射的光的输出引导到光波导（WG）图案层的接收光或从光波导（WG）图案层输入。 在平面图中为圆环状，圆形或多边形的金属膜从规定范围内从基于通孔的位置的中心蒸镀。 锥体或金字塔形模具被冲压到中心。 通过形成的锥形结构校正光的方向，以增加准确性的公差并减少光损失。

    Creation of combination of studs used for high-precision alignment between multiple chips
    5.
    发明专利
    Creation of combination of studs used for high-precision alignment between multiple chips 审中-公开
    创建用于多个CHIPS之间的高精度对齐的项目组合

    公开(公告)号：JP2013115135A

    公开(公告)日：2013-06-10

    申请号：JP2011258013

    申请日：2011-11-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： SAKUMA KATSUYUKI ,  TORIYAMA KAZUSHIGE ,  SUEOKA KUNIAKI ,  OBARA SAYURI

    IPC: H01L21/60

    CPC classification number: H01L24/81 ,  H01L2924/15787 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To realize high-precision alignment expected between a plurality of chips or between a substrate and chips.SOLUTION: A combination of a plurality of studs is created for regulating relative movement of a plurality of chips in a lateral direction in the case where a solder bump is melted between the plurality of chips. For each of the plurality of chips, the combination of the plurality of studs having a predetermined width is created at a position where any solder bump is defined as a reference in the arrangement of a plurality of solder bumps disposed between the plurality of chips in accordance with a pitch of the plurality of solder bumps in such a manner that the plurality of solder bumps set to each of the plurality of chips are aligned within a predetermined range by regulating the relative movement of the plurality of chips even in the case where the plurality of chips are moved relatively to each other by melting of the plurality of solder bumps.

    Abstract translation: 要解决的问题：实现在多个芯片之间或在基板和芯片之间预期的高精度对准。 解决方案：在多个芯片之间熔化焊料凸块的情况下，产生多个螺柱的组合以调节多个芯片在横向方向上的相对运动。 对于多个芯片中的每一个，在具有预定宽度的多个螺柱的组合中产生一个位置，在这样一个位置处，在根据设置在多个芯片之间的多个焊料凸块的布置中将焊料凸点定义为基准 以多个焊料凸块的间距，使得设置为多个芯片中的每一个的多个焊料凸块通过调节多个芯片的相对移动而在预定范围内对准，即使在多个芯片中的多个 芯片通过多个焊料凸块的熔化相对移动。 版权所有（C）2013，JPO＆INPIT

    Device on array arrangement for using partially different solder bump in array consisting of plural solder bumps
    6.
    发明专利
    Device on array arrangement for using partially different solder bump in array consisting of plural solder bumps 审中-公开
    在使用部分不同焊接块的阵列装置上设置的装置包括多个焊锡枪

    公开(公告)号：JP2013105951A

    公开(公告)日：2013-05-30

    申请号：JP2011249848

    申请日：2011-11-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： SAKUMA KATSUYUKI ,  TORIYAMA KAZUSHIGE ,  OBARA SAYURI

    IPC: H01L21/60

    Abstract: PROBLEM TO BE SOLVED: To attain solder bump connection with low stress so as to reduce stress to be applied on a silicon chip even in structure that a low-k material with low (fragile) mechanical strength is used for an interlayer insulation film of the silicon chip.SOLUTION: A square silicon chip (with thickness of 725 μm) and a laminate layer (with thickness of 1000 μm) are connected with each other by hardening after melting of a plurality of two-dimensionally arranged solder bumps between the square silicon chip and the laminate layer via a low-k layer (insulation layer of a wiring layer (BEOL)) which is arranged on the square silicon chip, and as a laminate, a plurality of partial solder bumps arranged from the circumference of the square silicon chip (equivalent to its four sides) to the inside to predetermined rate are adjusted by putting fillers to them so that degrees of elasticity become relatively lower than those of plurality of solder bumps at other parts.

    Abstract translation: 要解决的问题：为了获得具有低应力的焊料凸块连接，以便减少施加在硅芯片上的应力，即使在具有低（脆性）机械强度的低k材料用于层间绝缘的结构 硅片片。 解决方案：在正方形硅之间的多个二维排列的焊料凸块熔化之后，通过硬化将一个方形硅芯片（厚度为725μm）和层叠层（厚度为1000μm）彼此连接在一起 芯片和层叠层经由布置在方形硅芯片上的低k层（布线层（BEOL）的绝缘层）形成，并且作为层叠体，从方形硅的圆周排列的多个部分焊料凸块 通过向其内部填充填充物来调节内部到相对于预定速率的芯片（相当于其四边），使得其他部分的弹性程度相对低于多个焊料凸块。 版权所有（C）2013，JPO＆INPIT

    Electronic package for millimeter wave semiconductor dies
    8.
    发明专利
    Electronic package for millimeter wave semiconductor dies 未知

    公开(公告)号：GB2515940A

    公开(公告)日：2015-01-07

    申请号：GB201417884

    申请日：2013-03-27

    Applicant: IBM

    Inventor： KAMINSKI NOAM ,  ELAD DANNY ,  SHUMAKER EVGENY ,  OKAMOTO KEISHI ,  TORIYAMA KAZUSHIGE

    IPC: H01L23/66

    Abstract: A mm Wave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mm Wave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mm Wave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss.

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