公开(公告)号：WO02058117A3

公开(公告)日：2003-08-28

申请号：PCT/EP0201049

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP ,  IBM FRANCE

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mu ) with a bottom etch stop layer (104), a composite bottom plate (110) having an aluminium layer below a TiN layer, an oxide capacitor dielectric (120), and a top plate (130) of TiN. The process involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract translation: 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以内）的区域，底部蚀刻停止层（104），在TiN层下方具有铝层的复合底板（110）， 氧化物电容器电介质（120）和TiN的顶板（130）。 该方法包括蚀刻顶板以留下电容器区域，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。

公开(公告)号：JPH11260798A

公开(公告)日：1999-09-24

申请号：JP1536899

申请日：1999-01-25

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  DOBUZINSKY DAVID M ,  MALINOWSKI JOHN C ,  NG HUNG Y ,  WISE RICHARD S ,  YU CHIENFAN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a method for anisotropic etching of a nitride layer on a substrate. SOLUTION: In this etching process, an etchant gas containing fluorohydrocarbon rich in hydrogen, oxidant and carbon source is used. It is preferable that the fluorohydrocarbon rich is hydrogen be CH3 or CH2 F2 , the carbon source be CO2 or CO, and the oxidant be O2 . It is preferable that the fluorohydrocarbon exsist in a gas of about 7-35 vol.%, the oxidant exsist in a gas of about 1-35 vol.%, and the carbon source exsists in a gas of about 30-92 vol.%.

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH11186243A

公开(公告)日：1999-07-09

申请号：JP28213898

申请日：1998-10-05

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a resist prescription which is capable of reducing blisters that are generated in a reactive ion etching process to increase the deposit of a resin by-product. SOLUTION: Gaseous fluorocarbon etchant is excited by energy large enough to generate a plasma of high density, wherein the ratio of carbon to fluorine of the etchant is at least 0.33. A resist 12 which is least blistered under the above conditions contains resin binder of terpolymer besides a usual optically active component, wherein the resin binder is composed of (a) a first unit which contains groups unstable to acid, (b) a second unit which does not contain reactive groups and hydroxyl groups, and (c) a third unit which is conducive to development by an aqueous developing agent. The resist, layer 12 on a silicon oxide layer 14 is patterned, and plasma of high density is introduced onto the silicon oxide layer 14, and at least an opening 18 is provided to the silicon oxide layer 14 by etching.

公开(公告)号：DE60218442D1

公开(公告)日：2007-04-12

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：DE60218442T2

公开(公告)日：2007-11-15

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：AT355614T

公开(公告)日：2006-03-15

申请号：AT02718080

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：DE69821458D1

公开(公告)日：2004-03-11

申请号：DE69821458

申请日：1998-11-19

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer. Preferably, the terpolymer is made up of about 70% 4-hydroxystyrene, about 20% styrene, and about 10% t-butylacrylate.