公开(公告)号：EP2024995A4

公开(公告)日：2013-07-03

申请号：EP07797764

申请日：2007-05-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L21/76283

公开(公告)号：JP2005150713A

公开(公告)日：2005-06-09

申请号：JP2004312244

申请日：2004-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NG HUNG Y ,  YANG HAINING S

IPC: H01L27/04 ,  H01L21/302 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device structure for achieving a high device performance and to provide a method of forming the semiconductor device structure. SOLUTION: There is provided an etch resistant liner which covers a side wall of a transistor gate stack and resides along a part of a substrate at a lower part of the transistor gate stack. The liner prevents a silicide formation of the side wall of the gate stack which generates an electric shortage, and determines a location of the silicide formation within source and drain regions inside the substrate at the lower part of the transistor gate stack. The liner also covers a resistor gate stack and prevents the silicide formation in or adjacent to the resistor gate stack. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于实现高器件性能的半导体器件结构，并提供形成半导体器件结构的方法。 解决方案：提供了一种覆盖晶体管栅极堆叠的侧壁的耐蚀刻衬里，并且在晶体管栅极堆叠的下部沿衬底的一部分存在。 衬垫防止产生电缺陷的栅叠层的侧壁的硅化物形成，并且在晶体管栅堆叠的下部确定衬底内的源极和漏极区内的硅化物形成的位置。 衬套还覆盖电阻器栅极堆叠并且防止在电阻器栅极叠层中或其附近的硅化物形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11260798A

公开(公告)日：1999-09-24

申请号：JP1536899

申请日：1999-01-25

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  DOBUZINSKY DAVID M ,  MALINOWSKI JOHN C ,  NG HUNG Y ,  WISE RICHARD S ,  YU CHIENFAN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a method for anisotropic etching of a nitride layer on a substrate. SOLUTION: In this etching process, an etchant gas containing fluorohydrocarbon rich in hydrogen, oxidant and carbon source is used. It is preferable that the fluorohydrocarbon rich is hydrogen be CH3 or CH2 F2 , the carbon source be CO2 or CO, and the oxidant be O2 . It is preferable that the fluorohydrocarbon exsist in a gas of about 7-35 vol.%, the oxidant exsist in a gas of about 1-35 vol.%, and the carbon source exsists in a gas of about 30-92 vol.%.

公开(公告)号：JP2007134718A

公开(公告)日：2007-05-31

申请号：JP2006303401

申请日：2006-11-08

Applicant: Chartered Semiconductor Mfg Ltd ,  Internatl Business Mach Corp ,  Samsung Electronics Co Ltd ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  サムスン エレクトロニクス カンパニー リミテッド ,  チャータード・セミコンダクター・マニュファクチャリング・リミテッド

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

IPC: H01L21/8238 ,  C23C16/34 ,  H01L21/318 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823807

Abstract: PROBLEM TO BE SOLVED: To provide a SMT (stress memory technique) for both of an nFET and a pFET.
SOLUTION: The method includes forming a tensile stress layer 120 over the nFET 104 and a compressive stress layer 122 over the pFET 106, annealing 150 to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer 122 may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include the one used in a temperature of approximately 400-1,200°C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET 106.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为nFET和pFET两者提供SMT（应力记忆技术）。 解决方案：该方法包括在nFET104上形成拉伸应力层120，在pFET 106上形成压应力层122，退火150以将应力记忆在半导体器件中并除去应力层。 压应力层122可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括在约400-1200℃的温度下使用的退火步骤。 高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET 106中。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：WO2007140288A3

公开(公告)日：2008-04-24

申请号：PCT/US2007069720

申请日：2007-05-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76283

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Abstract translation: 本发明涉及具有器件区域（2,4,6）的绝缘体上绝缘体（SOI）衬底，每个衬底半导体衬底层（12）和半导体器件层（16）和掩埋绝缘体层（14） ）之间。 由垂直绝缘柱（22）支撑的半导体器件层（16）各自具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由垂直绝缘柱（ 22）。 气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

公开(公告)号：SG132607A1

公开(公告)日：2007-06-28

申请号：SG2006077119

申请日：2006-11-08

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD

Inventor： FANG SUNFEI ,  KIM JUN JUNG ,  LUO ZHIJIONG ,  NG HUNG Y ,  ROVEDO NIVO ,  TEH YOUNG WAY

Abstract: A method for providing a dual stress memory technique in a semiconductor device (100) including an nFET (104, 204) and a pFET (106, 206) and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer (120) over the nFET (104) and a compressive stress layer (122) over the pFET (106), annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

公开(公告)号：SG151256A1

公开(公告)日：2009-04-30

申请号：SG2009016890

申请日：2006-09-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WAY TEH YOUNG ,  SUNFEI FANG ,  ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  JUNG KIM JUN

Abstract: DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200[err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET. (Figure 6)

公开(公告)号：SG138522A1

公开(公告)日：2008-01-28

申请号：SG2007030810

申请日：2007-04-27

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  NGUYEN PHUNG T ,  WILLE WILLIAM C ,  LINSAY RICHARD ,  LUN ZHAO ,  FU CHONG YUNG ,  PANDA SIDDHARTHA

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

公开(公告)号：SG132585A1

公开(公告)日：2007-06-28

申请号：SG2006064562

申请日：2006-09-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SUNFEI FANG ,  JUNG KIM JUN ,  ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  WAY TEH YOUNG

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.