公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：JP2007133394A

公开(公告)日：2007-05-31

申请号：JP2006294934

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CULP JAMES A ,  LARS W LIEBMAN ,  MALIK RAJEEV ,  MULLER K PAUL ,  NARASIMHA SHREESH ,  RUNYON STEPHEN L ,  WILLIAMS PATRICK M

IPC: G03F1/08 ,  H01L21/82

CPC classification number: G06F17/5068

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving the yield, performance and timing of an integrated circuit. SOLUTION: An iterative timing analysis is performed analytically before a chip is fabricated, based on a technique that uses optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time-sensitive devices. An additional mask is used as a selective trim, to form shortened gate lengths or wider metal lines for selected predetermined transistors, affecting threshold voltages and RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. This analysis methodology is repeated as often as needed, to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants, until manufacturing limits are reached. A mask is made for the selected critical devices by using OPC techniques. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于提高集成电路的产量，性能和时序的方法。 解决方案：基于使用光学邻近校正技术缩短栅极长度和调整关键时间敏感器件的金属线宽度和接近距离的技术，在芯片制造之前分析地执行迭代时序分析。 使用附加掩模作为选择性修整，以形成选定的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 该分析方法根据需要经常重复，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为选定的关键设备制作掩码。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：WO2004027824A2

公开(公告)日：2004-04-01

申请号：PCT/US0329085

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

Inventor： SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L

CPC classification number: H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

Abstract: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

Abstract translation: 提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34） 在氮化钨层上形成含钨层和钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：WO0231878A3

公开(公告)日：2002-10-31

申请号：PCT/US0126644

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JAIPRAKASH VENKATACHALAN ,  MANDELMAN JACK ,  DIVAKARUNI RAMACHANDRAR ,  MALIK RAJEEV ,  SEITZ MIHEL

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: An array top oxide is protected in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays by a protective etch stop layer (18) which protects the top oxide (16) and prevents word line to substrate shorts and/or leakage. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor polysilicon (17) of the vertical MOSFET to the top surface of the top oxide (16). A thin polysilicon layer (18) is deposited over the planarized surface and an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches (20).

Abstract translation: 在通过保护顶部氧化物（16）的保护性蚀刻停止层（18）制造垂直金属氧化物半导体场效应晶体管（MOSFET）动态随机存取存储器（DRAM）阵列中的阵列顶部氧化物被保护，并且防止字线 衬底短路和/或泄漏。 包括垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体多晶硅（17）平坦化到顶部氧化物（16）的顶表面进行。 在平坦化表面上沉积薄多晶硅层（18），并沉积有源区（AA）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 使用AA掩模将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽（20）。

公开(公告)号：WO0198563A3

公开(公告)日：2002-05-30

申请号：PCT/US0119077

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： TEWS HELMUT HORST ,  FALTERMEIR JOHNATHAN E ,  MALIK RAJEEV ,  HEENAN CAROL ,  GLUSCHENKOV OLEG

IPC: C30B29/06 ,  C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L21/28185 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/973

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate (step 100) where surfaces have at least two different crystallographic orientations of the silicon crystal (step 102). Atomic oxygen (O) is formed for oxidizing the surfaces (step 106). An oxide is formed (step 108) on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract translation: 根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中表面具有硅晶体的至少两个不同晶体取向的衬底（步骤100）（步骤102 ）。 形成氧化表面的原子氧（O）（步骤106）。 通过使原子氧与表面反应，在表面上形成氧化物（步骤108），同时在表面上形成基本均匀的氧化物厚度。

公开(公告)号：DE10361273A1

公开(公告)日：2004-07-22

申请号：DE10361273

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： LI WAI-KIN ,  MALIK RAJEEV ,  MEZZAPELLE JOSEPH

IPC: G03C5/00 ,  G03F7/09 ,  G03F7/11

公开(公告)号：DE10393309T5

公开(公告)日：2005-12-29

申请号：DE10393309

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CABRAL CYRIL JR ,  IGGULDEN ROY C ,  MCSTAY IRENE LENNOX ,  CLEVENGER LAWRENCE A ,  WANG YUN YU ,  WONG KEITH KWONG HON ,  ROBL WERNER ,  GLUSCHENKOV OLEG ,  MALIK RAJEEV ,  SCHUTZ RONALD J

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：AU2003273328A8

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.