公开(公告)号：DE3172643D1

公开(公告)日：1985-11-14

申请号：DE3172643

申请日：1981-12-23

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  STADLER EWALD

IPC: H01L23/12 ,  H01L23/538 ,  H01L23/58 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K3/46 ,  H01L23/14 ,  H01L23/52 ,  H01L23/56

Abstract: This invention concerns a ceramic substrate for mounting semiconductor integrated circuits. The substrates include at least a first and second patterned metallization layer which respectively form conducting planes that are parallel to each other but separated by a thickness of insulation. The pattern metallization of at least the first plane includes signal conductors for joining the contacts of the integrated circuit chip to pins provided in the substrate for connecting the substrate and chip to a circuit board. In accordance with the invention, the metallization of the second plane includes shorted conductor loops that follow the contour of the signal conductors. The shorted loops of the second plane metallization includes branches which extend parallel to both lateral sides of a respective signal conductor. In accordance with the invention, the branches of the loops are joined at their ends.

公开(公告)号：DE3621469A1

公开(公告)日：1988-01-07

申请号：DE3621469

申请日：1986-06-26

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  VOGEL ARMIN ,  WAGNER OTTO DIPL ING ,  ZUEHLKE RAINER DR ING

IPC: G01R31/30 ,  G01R31/3185 ,  G01R31/28 ,  H01L21/66

Abstract: A multiplicity of gate elements (gate arrays) which are arranged like a matrix are connected by means of their line outputs and by means of their column outputs to an oscillator circuit, whose first output is connected to all the column inputs and whose second output is connected to all the row inputs. In the event of defective gate elements, said elements are localised in that, during the detection of a defective gate element row, the gate element rows orthogonal thereto are selected successively via their address and via a signal data input. The gate element row located in front of and behind a defective gate element row is determined by oscillator loops. The individual gate elements consist of a plurality of gates and make it possible to change a signal flow from a line into a column and vice versa. This makes possible signal flow diversion which simplifies fault localisation and its representation in the course of a display.

公开(公告)号：DE2940593A1

公开(公告)日：1981-04-16

申请号：DE2940593

申请日：1979-10-06

Applicant: IBM DEUTSCHLAND

Inventor： KRUMM HORST DIPL PHYS DR ,  SCHETTLER HELMUT DIPL ING ,  ZUEHLKE RAINER DIPL ING DR

IPC: H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14

Abstract: Disclosed is a multi-layer module structure having a constant characteristic impedance. In each conductor line plane, two signal lines are arranged between a ground and a voltage supply line. This line sequence: ground/signal/signal/voltage supply line, is repeated several times in each conductor line plane. The spacing between the signal line and the adjacent ground and voltage supply line, respectively, is identical in each case. Adjacent conductor line planes, nth and (n+1)th have conductor lines arranged orthogonally. The lines of the nth and the (n+2)th plane are preferably staggered to each other such that when the nth plane is projected relative to the (n+2)th plane, the ground line of the (n+2)th plane is arranged in between the voltage supply lines (e.g. a voltage supply line and a ground line) of the nth plane.

公开(公告)号：DE2855724A1

公开(公告)日：1980-07-03

申请号：DE2855724

申请日：1978-12-22

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  BROSCH RUDOLF DR ING ,  ZUEHLKE RAINER DR ING ,  SCHUMACHER HANS DR RER NAT

IPC: H03K19/0175 ,  G05F1/46 ,  H03K5/00 ,  H03K5/13 ,  H01L21/12 ,  H01L23/56 ,  G06F7/48

Abstract: For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference DELTA t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.

公开(公告)号：DE2719462A1

公开(公告)日：1977-12-08

申请号：DE2719462

申请日：1977-04-30

Applicant: IBM DEUTSCHLAND

Inventor： HOWARD DONALD DUNBAR ,  SCHETTLER HELMUT DIPL ING

IPC: H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K5/12

Abstract: An improved speed up circuit, especially useful with high speed, push pull circuits, is disclosed. This uses only A.C. power to discharge the interelectrode and depletion capacitances of an output transistor thereby eliminating uncontrolled shunt current from the output to ground through the output transistor thereby allowing the output to reach the desired level in a shorter period of time. These desirable results are accomplished by capacitively coupling a resistor-transistor speed up circuit to the base of the output transistor to actively pull the base of the output transistor to ground and discharge the inherent interelectrode and depletion capacitances of the output transistor.

公开(公告)号：DE3675925D1

公开(公告)日：1991-01-10

申请号：DE3675925

申请日：1986-02-21

Applicant: IBM DEUTSCHLAND

Inventor： LOEHLEIN WOLF-DIETER ING GRAD ,  SCHETTLER HELMUT DIPL ING ,  WAGNER OTTO DIPL ING

IPC: G11C11/34 ,  G11C11/409 ,  G11C11/412 ,  G11C11/419

公开(公告)号：DE2916854A1

公开(公告)日：1980-11-06

申请号：DE2916854

申请日：1979-04-26

Applicant: IBM DEUTSCHLAND

Inventor： SCHETTLER HELMUT DIPL ING ,  REMSHARDT ROLF DIPL ING ,  BROSCH RUDOLF DIPL ING ,  ZUEHLKE RAINER DR ING

IPC: H01L27/02 ,  H01L21/70 ,  G11C5/00 ,  H01L23/56 ,  H01L27/10

Abstract: The semiconductor chip integrated circuit with a control amplifier supplying a constant current, has two bipolar NPN transistors (T1, T2) with emitters connected. The collector of one transistor (T2) is connected by a resistance (R3) to the supply voltage (V1) which is directly connected to the other collector. The base of the first transistor (T1) is connected to the base of a third transistor (T3) with a Schottky diode (D1) between its base and collector, forming an input stage. The junction between the resistance (R3) and the second transistor (T2) is also connected to the base of an emitter follower transistor (T5). This has its output connected to two further transistor stages. The circuit may be used with logic or memory chips.

公开(公告)号：DE68927931D1

公开(公告)日：1997-05-07

申请号：DE68927931

申请日：1989-07-26

Applicant: IBM

Inventor： GANSAUGE PETER DR ,  KREUTER VOLKER DIPL ING ,  SCHETTLER HELMUT DIPL ING

IPC: H01L21/60 ,  H01L21/48 ,  H05K1/11 ,  H05K3/06 ,  H05K3/24 ,  H05K3/38

Abstract: An integrated circuit chip packaging structure comprising a substrate (10), preferably a semiconductor base substrate, a conductive layer (20) on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls (36) and gold bumps (34) connected to said conductive layer in said regions of said conductive layer, and a solder stop layer (22) on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines (30). Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus one metallization layer is prevented. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus packaging of VLSI circuits is improved.

公开(公告)号：DE68926886D1

公开(公告)日：1996-08-29

申请号：DE68926886

申请日：1989-09-15

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  SCHULZ UWE ,  ZUEHLKE RAINER DR ING

IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

公开(公告)号：DE68916784T2

公开(公告)日：1995-01-05

申请号：DE68916784

申请日：1989-04-20

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  LUDWIG THOMAS DIPL ING ,  WAGNER OTTO M DIPL-ING ,  HAUG WERNER O DIPL ING ,  KLINK ERICH ,  KROELL KARL E DIPL-PHYS ,  STAHL RAINER DIPL ING

IPC: H01L21/60 ,  H01L23/14 ,  H01L23/64

Abstract: Integrated circuit package comprising at least one active integrated circuit chip (1) mounted and electrically connected to a power supply distribution wiring and a chip interconnection and signal wiring both formed on the topsurface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5, 6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.